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Adventurer
Adventurer
499 Views
Registered: ‎08-26-2017

Zynq 7000 SD CARD : Boot and File Access Issue

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Hi,

We have developed a custom video card using Zynq 7000 part XC7Z020-2CLG484. We have two revisions of it. In the second version of this we are facing issues with SD card interface. We could not get the system up when we use SD card boot. We had copied the section as is from our version 1, where everything worked very well.

More Details:

1) The system works very well in JTAG mode. We could program FPGA and load our application from SDK and test the basic functioanlities of the system i.e., video capture from sensor and display it on multiple video out ports. This confirms that there are no issues with power up and power up sequence. Our design is based on ZC702 and we used the same power supply section in our design elimianting the need for possible power seqeuncing issues. There is a small change though. ZC702 uses 3 UCDs, we have used only 2 UCDs and the mapping of rails of these two UCDs is same as that of U52 and U53 of ZC702. 

To rule out the 1.8v and 3.3v power supply sequence impact on SDcard circuit, we have also tried a different sequence where all PL supplies go up first followed by PS providing enough delay between 3.3v and 1.8v used in SD card ckt. Results are same. 

2) We tried the same SD card (with BOOT.bin) with our version 1 and that boots up well. FPGA gets configured as expected. This confirms the integrity of BOOT.bin we used. 

3) We have used the SD card test example given with SDK xilffs_polled_example.c to test if SD card file access works well. Well, the application runs but flow gets stuck in a while loop where it checks for the status of cmd and data signals.

4) We have probed the sd clk line in both working and non working versions. In the working version, we see that the SD CLK ticks at the rate of 14-15 MHz at power up and stabilises at 50MHz after boot. In non working board , we are seeing that SD clk ticks at 200KHz and stops giving any clock after a while, typically 3-5 seconds. 

5) Referring to few older posts regarding this,

     a) we have tried adding DEBUG into FSBL and see if we get any debug prints. Sadly, we do not get any.

     b) We have tried reading the register 0xF8000258 from XSCT. I get the value 0x0040200A. Referring to UG 585 table 6-20, as given in ERROR CODE.jpg, i verified the mode pins and could see that they are mapped properly. I could not however verify the other three conditions though.

 

Can anyone through light on what could be going wrong here? 

 

Thanks and Regards,

Ajay Kumar G    

ERROR CODE.jpg
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1 Solution

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Xilinx Employee
Xilinx Employee
463 Views
Registered: ‎10-11-2011

Re: Zynq 7000 SD CARD : Boot and File Access Issue

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"we are seeing that SD clk ticks at 200KHz and stops giving any clock after a while, typically 3-5 seconds".

I would recommend to look at the CMD line and trying to understand if it's the card not responding or the zynq non seeing the response. I did see card in the past not responding if DAT lines where not properly pulled up even if the initial communication is over CMD only.

At this point I really think you need to identify the command that is failing.

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3 Replies
Adventurer
Adventurer
480 Views
Registered: ‎08-26-2017

Re: Zynq 7000 SD CARD : Boot and File Access Issue

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To add to details,

I have tried to read PS internal registers related to SD card status and clock control. 

Read SD PRESENT STATE REG @ 0xE0100024 -> 01FF0000

          Implies CMD and DAT lines are error free, Write Enabled, Card Detected, is inserted and is stable

Read SD Clock Control, Time Out and SW RST @ 0xE010002C -> 000A0103 

          Implies Data Time Out counter set to 2^23, SDCLK Freq selected to base clk/2, Internal oscillator is enabled and stable, SD clk is disabled.

Write SD Clock Control @ 0xE010002C -> 000A0107

          SD CLK enabled. Resulted in a 25MHz clk output on SD CLK line. 

          In this case, the xilffs_polled_example runs a little further and stops. It fails to create partition in the drive and throws an error.

Description given to SD_CLOCK_ENABLE BIT : The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then, the HC shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK = 0). If the HC detects the No Card state, this bit shall be cleared.
1 - Enable
0 - Disable

If HC detects a no card state it clears SD CLK ENABLE, but read SD PRESENT STATE REG shows that Card is detected and is stable. So, what else could be disabling this bit?

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Xilinx Employee
Xilinx Employee
464 Views
Registered: ‎10-11-2011

Re: Zynq 7000 SD CARD : Boot and File Access Issue

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"we are seeing that SD clk ticks at 200KHz and stops giving any clock after a while, typically 3-5 seconds".

I would recommend to look at the CMD line and trying to understand if it's the card not responding or the zynq non seeing the response. I did see card in the past not responding if DAT lines where not properly pulled up even if the initial communication is over CMD only.

At this point I really think you need to identify the command that is failing.

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Adventurer
Adventurer
440 Views
Registered: ‎08-26-2017

Re: Zynq 7000 SD CARD : Boot and File Access Issue

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Hi @denist 

Thank you. The 3.3v VDD to SD card connector has a 0Ohm resistor in series. A 10KOhm resistance has been mounted by mistake and this caused the VDD to drop to 3V. We replaced the resistance with proper value and that has solved the issue for us.

Marking the solution as accepted and closing this issue.

Thanks

Ajay Kumar

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