02-05-2020 08:47 PM
Hi, dear Xilinx's experts,
I have a question about Zynq-7000 SRST and POR Signals release Sequencing on power on when I designning a project.
My project use XC7Z045 series chip. When I was reading UG585, I'm a little confused. Accoding to page 164 figure 6-4,
PS_SRST_B is de-asserted before PS_POR_B being de-asserted(Pulling High). But according to page 711,Figure 26-3:
It is seems like PS_SRST_B is de-asserted after PS_POR_B being de-asserted for a ram memory clear.
So the what is the suggestted sequence I should follow?
Thank you for your advance!
02-06-2020 09:55 PM
You can tie PS_SRST_B permanently high and it will work fine.
Typically SRST is just used for debugging. For example, on my boards I tie it to a pullup resistor and the JTAG header and ESD protection and nothing else.
I use PS_POR_B to reset the board. This is derived from the power supply supervisor(s). This does not need to connect to SRST.
02-08-2020 09:16 PM
Hi ,thank you so much for your answer and detailed explaination! On my board I also tie SRST to a pullup resistor. I want to ask you more about this question if you don't mind.
On my board, the voltage of bank PS 500 where PS_POR_B locates in is 3.3V, the he voltage of bank PS 501 where PS_SRST_B locates in is 2.5V.
During different power supply squencing power on, should 2.5V power on before 3.3V or after or it doesn;t matter?
Thanks for your help
02-08-2020 09:18 PM
05-25-2021 01:22 AM
Could you tell me why the PS_POR_B asserted doesn't erase the PL bitstream if I have PS_SRST_B floating or pulled up ?
In fact only PS_SRST_B asserted reset my bitstream whatever PS_POR_B status.