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Visitor
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Registered: ‎09-09-2018

Zynq 7000 Unable to boot without PL power

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Hi,

We are running into some weird issues with out Zynq-7030 board. We have separated the PL/PS power supply so that on power-up only the PS powers up, which then in turn can power up the PL on demand. Based on this paragraph from the TRM I think this should be possible:

PL Initialization and Configuration

The PL must be powered-up before it can be initialized and then configured with the bitstream. The power-up and bring-up stages of the PL operate independently of the PS, but PL power up needs to maintain a certain timing relationship with the POR reset signal of the PS. For more details refer to section 6.3.3 BootROM Performance: PS_POR_B De-assertion Guidelines, page 179.

The PL can be under the control of FSBL/User code using GPIOs or serial interfaces to external devices. Internally, the BootROM and FSBL/User code can determine the state of the PL power. FSBL/User code can receive interrupts when the PL power state changes.

We are however a bit confused by some things like:

PL power is needed for PCAP access and image decryption. The BootROM tests the PL state before accessing its resources using a 90 second timeout. The PROGRAM_B device pin must be held High during the boot process. Holding the PROGRAM_B device pin Low during the boot process causes a device lockdown event.

If I understand correctly bank 0 and all associated configuration pins are part of the PL power domain. Our power sequence is as follows:

  • V_PS_VCCINT_1P0
  • V_PS_VCCAUX_1P8
  • V_PS_VCCO_3P3
  • V_EMMC0_VCC_3P3 (Power good toggles POR)

Then (initiated by PS):

  • V_PL_VCCINT_1P0
  • V_PL_VCCAUX_1P8
  • V_PL_VCCO_1P8
  • V_MGT_VTT_1P2

When we sequence PL+PS at the same time the board starts up fine, but when we disable the PL power the device will not boot up. Does anyone have an idea what we are doing wrong? We already looked and made sure there is no interaction with the PL during boot.

Thanks!
Joris

power.pngbank0.pngconfig.png

ps.png

 

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Visitor
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Registered: ‎09-09-2018

Re: Zynq 7000 Unable to boot without PL power

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After more investigation I found some noise on the 1V0 and 1V8 rails when the rails were shut down.

pl-reg.png

After changing the LTM4628 from force continuous mode to pulse-skipping mode of operation the problem magically went away. I think this can be explained by the lack of current load of the PL the voltage rail got unstable.

Thanks everyone for thinking along. The fact that nobody pointed out something obvious allowed me to focus more on the power supplies.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: Zynq 7000 Unable to boot without PL power

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Are you use any sort of secure boot? I believe VCC for BANK 0 needs to be powered in order to get proper status for bootROM to execute. Can you try to move it to the rest of the PS voltages?

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Registered: ‎01-22-2015

Re: Zynq 7000 Unable to boot without PL power

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@joris-hiber 

Perhaps the following from pages 86-87 of UG470(v1.13.1) describes the problem:

The power supplies should ramp monotonically within the power supply ramp time range specified in the respective 7 series FPGAs data sheet. All supply voltages should be within the recommended operating ranges; any dips in VCCINT below VDRINT or VCCAUX below VDRI (see the respective 7 series FPGAs data sheet for specific values) can result in loss of configuration data.  If a monotonic ramp is not possible, delay configuration by holding the INIT_B Low (see Delaying Configuration) while the system power reaches the minimum recommended operating voltages for VCCO_0, VCCAUX, VCCBRAM, and VCCINT.

That is, when PL power-up is controlled by PS-side, are PL-side power rails coming up monotonically and within the ramp times specified in DS191 datasheet for your device?  -and is INIT_B being held low long enough?

Also note that problems can occur when external devices with IO connections to the PL side of the FPGA are powered up before VCCO of the FPGA.  See the following links for more information.
https://www.xilinx.com/support/answers/45985.html
https://www.xilinx.com/support/answers/37347.html

Mark

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: Zynq 7000 Unable to boot without PL power

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DO NOT held INIT_B in zynq devices. It is NOT the right way to delay configuration.

The bootROM uses INIT_B to determine if he can proceed.

Holding INIT_B hangs the bootROM after a timeout inside.

DO NOT held INIT_B in zynq devices, hold PS_POR_B instead.

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Registered: ‎01-22-2015

Re: Zynq 7000 Unable to boot without PL power

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@denist 

Thank you for the correction.  However, I hope you'll agree that the rest of my post identifies valid concerns about power-up of the PL side of the Zynq.

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Xilinx Employee
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Registered: ‎10-11-2011

Re: Zynq 7000 Unable to boot without PL power

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I agree. The concerns are valid.

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Visitor
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Registered: ‎09-09-2018

Re: Zynq 7000 Unable to boot without PL power

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Thanks all for the suggestions. To be clear, the problem only arises when PL is completely un-powered, so pins like INIT_B are not relevant if I understand correctly.

 

This is what the PS rails look like with PL Powered and things work as expected:

pl-ok.png

 

However when I disable PL power I get the follow random reboot cycle.

pl-bad.png

 

PS_VCCINT current limit is set to 300mA (600mA for short duration) which should be sufficient according do DS191. Is there any reason it could be using significantly more power when PS is disabled? I looked at all PL rails and it does not look like I am backfeeding it anywhere.

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Registered: ‎09-09-2018

Re: Zynq 7000 Unable to boot without PL power

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After more investigation I found some noise on the 1V0 and 1V8 rails when the rails were shut down.

pl-reg.png

After changing the LTM4628 from force continuous mode to pulse-skipping mode of operation the problem magically went away. I think this can be explained by the lack of current load of the PL the voltage rail got unstable.

Thanks everyone for thinking along. The fact that nobody pointed out something obvious allowed me to focus more on the power supplies.

 

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Visitor
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Registered: ‎03-22-2020

Re: Zynq 7000 Unable to boot without PL power

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Hi Joris,

Did you managed to power up your IC eventually (PS Only)?

The problem was infact the power supplies (and once corrected, the power up went well).

I'm currently designing a board based on XC7Z020 and i also want to have the ability to power up the PS only, or both.

 

 

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Visitor
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Registered: ‎09-09-2018

Re: Zynq 7000 Unable to boot without PL power

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Hi EyalBar. I did! After I fixed by power supply all issues were resolved.

You should take some extra care around Bank0 and other configuration pins (including JTAG) that are all on PL, maybe this sounds obvious but I somehow had these on the PS domain on my first revision.

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Registered: ‎03-22-2020

Re: Zynq 7000 Unable to boot without PL power

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Thanks!

What exactly do you mean?

bank0 is in PS power domain (MIO0..15) - or do you refer to something else?

I also put the other pins in the PS domain - should i connect them to the PL Power domain?

Pins like PROGRAM_B, INIT_B, CFG_BVS and DONE_0 should be connected to PL power domain?

 

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Registered: ‎09-09-2018

Re: Zynq 7000 Unable to boot without PL power

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The MIO pins are on Bank 500 and 501, those are indeed PS domain.

JTAG and PROGRAM_B, INIT_B, CFG_BVS and DONE_0  are on Bank 0 (So PL Power)

Also be aware that JTAG will only function with PL Power. Secure boot options also rely on PL power.