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doner_t
Explorer
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Registered: ‎04-19-2016

Zynq-7000 supported Max QSPI Flash size

Hello,

 

In the Zynq UG585 TRM, it is written that Quad-SPI linear address for linear mode is FC00_0000 to FDFF_FFFF.  If I were use two QSPIs in dual-parallel mode, this address range means that I could use at most 32MB QSPI flash in dual-parallel mode? 

 

Thank you,

Best Regards,

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bpatil
Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @doner_t,

 

Check for https://www.xilinx.com/support/answers/50991.html (Configuration and Specifications)

 

Regards,

Bhushan

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doner_t
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Registered: ‎04-19-2016

Dear @bpatil,

 

I have checked the AR# 50991. It is seen that Zynq-7000 series support the up to 32MB configuration flash in the QSPI - Dual Parallel Memory. Isnt it ? 

 

Now, a Dual-parallel QSPI flash (each one is 32MB, as total 64MB) is connected to the Zynq (xc7z100). So in this case, we can not use the 32MB portion of the entire 64MB memory? Or, any other possible problem about the this case? i.e :  in SW, we can not write first 30-40 bytes of the this QSPI. Does 64MB dual-parallel QSPI flash cause the this problem in SW? 

 

Best Regards,  

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bpatil
Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @doner_t

 

It is seen that Zynq-7000 series support the up to 32MB configuration flash in the QSPI - Dual Parallel Memory. Isnt it ? 

> Yes!!

QSPI Zynq.JPG

 Does 64MB dual-parallel QSPI flash cause the this problem in SW? 

> Check https://www.xilinx.com/support/answers/47500.html  

and

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-7030-Can-t-program-QSPI-Flash/td-p/367869

 

 

Regards,

Bhushan

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Regards,
Bhushan

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doner_t
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Registered: ‎04-19-2016

Hello @bpatil,

 

*I have read the these posts and QSPI controller in the Zynq -TRM. 

*Controller is 24-bit address capable, so it can address up to 16MB. and in dual-parallel mode, it can address up to 32MB.

*However, cannot see anything about the what is effect of usage QSPI flash larger than 32MB.

*I should revised problem that we can not read first 64Bytes and cannot write to first 4Bytes of the QSPI (FC00_0000). I dont know whether this problem is related to the 64MB QSPI in dual-parallel while it should be 32MB at most.

 

Best regards,

  

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bpatil
Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @doner_t

 

Check https://www.xilinx.com/support/answers/57744.html

 

Regards,

Bhushan

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Regards,
Bhushan

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denist
Xilinx Employee
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Registered: ‎10-11-2011

If you can't read in linear mode FC00_0000 is because of the way the zynq manages the Read data.

See UG585 "Read Data Management" on page 349.

Is the same reason why "https://www.xilinx.com/support/answers/57900.html" require special attention.

 

Xilinx uses IO Mode (and the EXTENDED ADDRESS register) to be able to manage > 16MB flashes.

 

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