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Observer
Observer
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Registered: ‎06-10-2010

Zynq UltraScale+ BootROM Single-QSPI MIO Configuration

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Hello,

 

When using the Zynq UltraScale+ MPSoC QSPI boot mode, according to the TRM v1.8 page 236 Table 11-1 MIO pins 0 through 12 are used. I understand all of them are required for dual QSPI setups, but when using a single QSPI the only pins really needed are MIO 0 through 5.

My question is, how does the BootROM configure the MIO pins? Does it start with setting up MIO[5:0], load a chunk of the bitstream and then check if it needs to switch to a dual configuration also setting up the remaining MIO pins? Or does it configure MIO[12:0] for QSPI right from the start?

How about MIO6, which seems only required by some clock feedback mode? Is it set up as an output by the BootROM?

 

We would like to connect circuitry unrelated to QSPI and booting to MIO pins 6 through 12 but are concerned the BootROM might set up some of these pins as outputs or get irritated by non-QSPI signal levels on inputs.

 

Any pointers to documentation or personal experience describing how the BootROM sets up QSPI for single device configurations are welcome.

 

Thanks, David

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Xilinx Employee
Xilinx Employee
1,533 Views
Registered: ‎10-11-2011

The ROM reads from the flash using MIO[6:0] first, then switch to a wider MIO[12:0] configuration only if it detects a specific pattern in the width detection field of the bootROM header.

The ROM will always use the same frequency to boot and the feedback clock won't change that.

You need the feedback clock if you want to run the QSPI interface at FSBL (and after) at > 40MHz.

 

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Community Manager
Community Manager
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Registered: ‎07-23-2012
There is a Width Detection value part of Boot header and CSUROM uses this parameter to determine the width of QSPI flash.

You need not connect the MIOs that aren't required for your configuration. If the QSPI frequency is less than 40 MHz, then you needn't use a feedback clock.
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Observer
Observer
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Registered: ‎06-10-2010

Hello smarell,

 

thank you for your answer!

 

Does your statement about width detection imply that only MIO[6:0] are used in a first step, and the BootROM switches to MIO[12:0] when it detects a wider configuration, or is it the other way round.

 

Regarding the feedback clock: I understand I don't have to connect it. But what if I connect it to something unrelated to QSPI? Will this have a negative effect? How do I know what QSPI frequency will be used by the BootROM?

 

Best regards, David

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Xilinx Employee
Xilinx Employee
1,534 Views
Registered: ‎10-11-2011

The ROM reads from the flash using MIO[6:0] first, then switch to a wider MIO[12:0] configuration only if it detects a specific pattern in the width detection field of the bootROM header.

The ROM will always use the same frequency to boot and the feedback clock won't change that.

You need the feedback clock if you want to run the QSPI interface at FSBL (and after) at > 40MHz.

 

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Observer
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Registered: ‎06-10-2010

Hello denist, thanks for your precise answer! Best regards, David

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