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Visitor kpilch
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368 Views
Registered: ‎01-29-2019

Zynq UltraScale+ CoreSight tracing with timestamps

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I have ZCU104 evaluation board and I am gathering CoreSight traces from embedded application (bare metal program running on Cortex-A53). I have a problem with gathering timestamps for the traces. I have managed to enable timestamps but they are not incrementing at all -- every timestamp I see is updated by 0x0, see decoded traces in the listing below:

Idx:2793; ID:10; [0x02 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x00 ];  I_TIMESTAMP : Timestamp.; Updated val = 0x0
Idx:2804; ID:10; [0xd4 ];       I_ATOM_F6 : Atom format 6.; EEEEEEEEEEEEEEEEEEEEEEEE
Idx:2777; ID:10; OCSD_GEN_TRC_ELEM_PE_CONTEXT((ISA=Unk) EL3S; 64-bit; VMID=0x0; CTXTID=0x0; )

I am debugging using JTAG. I tried to power on the clock that I think is used for generating timestamps -- I used XilPm library and tried to power on this clock 'PM_CLOCK_TIMESTAMP_REF' but I got "NO ACCESS" error both for setting and getting clock state. So I tried to request APU_1 core with PMU (program is running on APU_0) with exactly the same result.

 

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Visitor kpilch
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330 Views
Registered: ‎01-29-2019

Re: Zynq UltraScale+ CoreSight tracing with timestamps

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Turned out I needed to turn on TimeStamp Generator (TSGEN) manually because it is not by default (which was a supprise for ARM community).

To do it, one has to set 'enable' bit in CNTCR (Counter Control Register of TSGEN) register. That is (at least in UltraScale+ case) 0th bit of CNTCR, which is register with offset 0 of the TSGEN.

In order to receive accurate timestamps in program trace, It is important to write accurate clock frequency to Base Frequency ID register (CNTFID0), as this is not set automatially (also, one can configure TSGEN input clock to different than default value).

Any further information can be found at ARM CoreSight SoC-400  Techical Reference Manual (DDI 0480F)

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Visitor kpilch
Visitor
331 Views
Registered: ‎01-29-2019

Re: Zynq UltraScale+ CoreSight tracing with timestamps

Jump to solution

Turned out I needed to turn on TimeStamp Generator (TSGEN) manually because it is not by default (which was a supprise for ARM community).

To do it, one has to set 'enable' bit in CNTCR (Counter Control Register of TSGEN) register. That is (at least in UltraScale+ case) 0th bit of CNTCR, which is register with offset 0 of the TSGEN.

In order to receive accurate timestamps in program trace, It is important to write accurate clock frequency to Base Frequency ID register (CNTFID0), as this is not set automatially (also, one can configure TSGEN input clock to different than default value).

Any further information can be found at ARM CoreSight SoC-400  Techical Reference Manual (DDI 0480F)

View solution in original post