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Contributor
Contributor
699 Views
Registered: ‎05-07-2018

Zynq UltraScale+ MPSoC VCU TRD 2019.1 - SDI Video Capture Project on a Custom Board Clock Error

Hello,

I'm trying to implement VCU TRD 2019.1 SDI Video Capture project on my custom board with XCZU5EV. I can run the project on ZCU106. There are several differences between my board and the zcu106:

1 - On ZCU106, SDI clock (U56, controlled via i2c) used in the project is connected to MGTREFCLK1 pins (U9 & U10) on Bank 226. On my board, there's a fixed clock (74.25 MHz) connected to MGTREFCLK0 pins (D9 & D10) on Bank 226.

2 - On ZCU106, SI RX/TX ports gtrxp, gtrxn, gttxp and gttxn are connected to AC2, AC1, AC6 and AC5 pins respectively on Bank 225. On my board, these pins are connected to D2, D1, D6 and D5 on Bank 226 (both are MGTHRX0 and MGTHTX0 pins).

3 - On ZCU106, GEM3 is used as ethernet controller. On my board, GEM1 is used. I haven't tested it yet.

4 - On ZCU106, SD1 is used as SD card controller. On my board, SD0 is used to control eMMC module. I haven't tested it yet.

5 - DDR rams are different on my board. I made changes on Zynq IP according to my DDR3 configuration. I could ran Zynq MP DRAM tests without any error on my board.

6 - QSPI interface is the same on both boards. I haven't tested QSPI flash yet.

7 - I disabled SATA, DisplayPort, USB, CAN and I2C on Zynq IP.

I used tcl script (vcu_sdirx_bd.tcl, provided in VCU TRD) to generate block design, then I made changes on Zynq IP. After bitstream generation and hardware exportation, I created a Petalinux project. The commands I used are:

petalinux-create --type project --template zynqMP --name peta_sdirx
petalinux-config --get-hw-description='.../vcu_sdirx/vcu_sdirx.sdk'
petalinux-build

Currently, I'm trying to boot from JTAG and I use these commands:

#Disable Security gates to view PMU MB target
targets -set -filter {name =~ "PSU"}

#By default, JTAGsecurity gates are enabled
#This disables security gates for DAP, PLTAP and PMU.
mwr 0xffca0038 0x1ff

#Load and run PMU FW
targets -set -filter {name =~ "MicroBlaze PMU"}
dow pmufw.elf
con

#Reset A53, load and run FSBL
targets -set -filter {name =~ "Cortex-A53 #0"}
rst -processor
dow zynqmp_fsbl.elf
con

stop

#Other SW...
dow u-boot.elf
dow bl31.elf
con

Terminal prints these:

#SERDES initialization timed out ==> After
NOTICE: ATF running on XCZU5EG/EV/silicon v4/RTL5.1 at 0xfffea000
NOTICE: BL31: Secure code at 0x60000000
NOTICE: BL31: Non secure code at 0x8000000
NOTICE: BL31: v2.0(release):xilinx-v2018.3-720-g80d1c790
NOTICE: BL31: Built : 03:34:50, Mar 9 2020
PMUFW: v1.1
zynqmp_clk_get_peripheral_rate mio read fail
failed to get rate
zynqmp_clk_get_peripheral_rate mio read fail
failed to get rate
zynqmp_clk_get_peripheral_rate mio read fail
failed to get rate
zynqmp_clk_get_peripheral_rate mio read fail
failed to get rate
zynqmp_clk_get_peripheral_rate mio read fail
failed to get rate
No serial driver found
### ERROR ### Please RESET the board ###

Apparently there are problems about the clocks in the design. What else I need to change in the design?

Thanks in advance.

0 Kudos
3 Replies
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Xilinx Employee
Xilinx Employee
599 Views
Registered: ‎10-11-2011

Be sure you have some dealy between FSBL start and stop to guarantee is running long enough to initialize the system.

dow zynqmp_fsbl.elf
con

after 5000

stop

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Highlighted
Contributor
Contributor
569 Views
Registered: ‎05-07-2018

Thanks for answering.

We write "after 5000" command between connection and stop steps. Actually we enter commands one by one manually ,so probably we already wait more than 5 seconds between steps.
Highlighted
Xilinx Employee
Xilinx Employee
495 Views
Registered: ‎10-11-2011

 I checked internally and found few reported issues with that error:

"

zynqmp_clk_get_peripheral_rate mio read fail

"

All the time was caused by either PMUFW not getting properly loaded or FSBL incorrect settings/mismatch version.

In your cause I believe something you changed is not playing along with the boot flow.

Can you try to introduce your changes one at the time to narrow down which one is causing this? 

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Don’t forget to reply, kudo, and accept as solution.
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