Zynq Ultrascale+ QSPI Support

[mhilley]

We are looking at using a ZYNQ Ultrascale+ MPSoC device.  I know you can configure the PS-QSPI interface as Dual Stacked which allows for 2 Devices.  Can a 3rd device be added to that bus, if I use a separate GPIO as a chip select for the 3rd device?  Or will the 3rd device need to be located in the PL on a separate Bus?

Thanks

[abommera]

Hi @mhilley,

The Quad-SPI controller can interface to one or two flash devices. Xilinx has not characterized using GPIO as a chip select. If you want to use the 3rd device in PL, you can access it by using AXI QSPI IP.