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tchin123
Voyager
Voyager
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Registered: ‎05-14-2017

Zynq require to program FPGA

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1) I'm using the ZCU106 development board that has the ZYNQ Ultrascale+ FPGA. Since my design is PL logic only, do I still need to include the Zynq into my design in order to Flash the QSPI device?

2) secondly, when testing the FPGA via JTAG, since downloading the PL logic bitstream is directly programming the FPGA, in this case do I also need to include the ZYNQ even though I'm not using it

3) Is the IPI block design the way to include the ZYNQ and my VHDL design

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ddn
Moderator
Moderator
113 Views
Registered: ‎06-06-2018

@tchin123 ,

1) I'm using the ZCU106 development board that has the ZYNQ Ultrascale+ FPGA. Since my design is PL logic only, do I still need to include the Zynq into my design in order to Flash the QSPI device?

>> Yes, FSBL is required to get configured from flash. Hence you need include Zynq processor.

2) secondly, when testing the FPGA via JTAG, since downloading the PL logic bitstream is directly programming the FPGA, in this case do I also need to include the ZYNQ even though I'm not using it

>>Directly you can generate BIT File without including Zynq and program the FPGA. Because PSU_INIT.TCL File will take care of all the initialization part.

 

3) Is the IPI block design the way to include the ZYNQ and my VHDL design

>> IPI Flow is the way to include Zynq.

Regards,
Deepak D N
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ddn
Moderator
Moderator
114 Views
Registered: ‎06-06-2018

@tchin123 ,

1) I'm using the ZCU106 development board that has the ZYNQ Ultrascale+ FPGA. Since my design is PL logic only, do I still need to include the Zynq into my design in order to Flash the QSPI device?

>> Yes, FSBL is required to get configured from flash. Hence you need include Zynq processor.

2) secondly, when testing the FPGA via JTAG, since downloading the PL logic bitstream is directly programming the FPGA, in this case do I also need to include the ZYNQ even though I'm not using it

>>Directly you can generate BIT File without including Zynq and program the FPGA. Because PSU_INIT.TCL File will take care of all the initialization part.

 

3) Is the IPI block design the way to include the ZYNQ and my VHDL design

>> IPI Flow is the way to include Zynq.

Regards,
Deepak D N
---------------------------------------------------------------------------
Please Kudo and Accept as a Solution, If it helps.
---------------------------------------------------------------------------

View solution in original post