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Registered: ‎08-30-2018

Zynq reset PS_POR assertion time

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Hello,

I am designing a base board to a Zynq XC7Z010 device. After reading the section 6.2.4 Reset Operations of the Technical Reference Manual and the section PS Switching Characteristics / Resets of the DS187 Zynq-7000 SoC DC and AC Switching Characteristcs I get a bit confused.

 

Technical Reference Manual says (highlights are mine):

PS_POR_B: The POR reset is the only reset to sample the boot mode pin strap resistors. For the power-up sequence, the PS_POR_B input is required to be asserted Low until V_CCPINT , V_CCPAUX and V_CCO_MIO0 have reached their minimum operating levels to ensure PS eFUSE integrity.

PS_SRST_B: This reset is used to force a system reset. It can be tied or pulled High, and can be High during the PS power supply ramp-up. The PS_SRST_B reset is a non-POR reset.

 

DS187 Zynq-7000 SoC DC and AC Switching Characteristcs presents table 22 and says:

table22.png

Note: 1. PS_POR_B needs to be asserted Low until T_PSPOR after PS supply voltages reach minimum levels.

 

Joining the informations about PS_POR signal, I imagine that the timings described by Table 22 are related to the power-up sequence and, therefore, the PS_POR should remain asserted low for a minimum of 100uS after the rising of  the signals described in the technical reference manual (V_CCPINT , V_CCPAUX and V_CCO_MIO0). Is that correct?

Moreover, if my understanding above described is correct, it means that in the power up sequence, the PS_SRST_B should be asserted low for the first 3 clock cycles after the rising of supply signals (V_CCPINT , V_CCPAUX and V_CCO_MIO0). But this is incosistent with what is pointed in the Technical Reference Manual, which says that this signal can be tied high during power up.

 

Could some one give me some clarification about the rigth sequence of assertion/de-assertion of signals PS_POR and PS_SRST_B during power-up?

 

Thanks in advance,

Luis

 

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Registered: ‎01-08-2012

Re: Zynq reset PS_POR assertion time

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Yes, exactly as described in DS187 Table 22 Note 1 (that you quoted in your first post).

In my experience, POR is always driven by some sort of "reset generator" or "supervisor" IC and they typically include a time delay of some ms, which easily meets the Zynq 100us requirement.

I assume you have already chosen, or are in the process of choosing a supervisor chip.  If not, Digikey lists some tens of thousands of them to consider:

https://www.digikey.com/products/en/integrated-circuits-ics/pmic-supervisors/691

The choice drops to about 10k if you use their filters to select ROHS, surface mount, active low reset output, not obsolete and timeout > 100us.

You are using a Zynq, which means you have at least three different voltages to monitor.  Note that it is sometimes less expensive to use multiple single-voltage monitors than it is to use a single multi-voltage monitor.

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Registered: ‎01-08-2012

Re: Zynq reset PS_POR assertion time

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You don't need to drive PS_SRST_B active during power-up, or at all! On some of my boards, PS_SRST_B is connected to a pullup resistor, the JTAG header, ESD protection, and nothing else.
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Registered: ‎08-30-2018

Re: Zynq reset PS_POR assertion time

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Thanks for your reply @allanherriman .

 

What about the other question? PS_POR need to wait for 100us to de-assertion after the rise of the supply lines?

 

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Registered: ‎01-08-2012

Re: Zynq reset PS_POR assertion time

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Yes, exactly as described in DS187 Table 22 Note 1 (that you quoted in your first post).

In my experience, POR is always driven by some sort of "reset generator" or "supervisor" IC and they typically include a time delay of some ms, which easily meets the Zynq 100us requirement.

I assume you have already chosen, or are in the process of choosing a supervisor chip.  If not, Digikey lists some tens of thousands of them to consider:

https://www.digikey.com/products/en/integrated-circuits-ics/pmic-supervisors/691

The choice drops to about 10k if you use their filters to select ROHS, surface mount, active low reset output, not obsolete and timeout > 100us.

You are using a Zynq, which means you have at least three different voltages to monitor.  Note that it is sometimes less expensive to use multiple single-voltage monitors than it is to use a single multi-voltage monitor.

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Registered: ‎08-30-2018

Re: Zynq reset PS_POR assertion time

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Thanks again @allanherriman!

I was just wanting to be sure about this line delay.

 

In addition, thanks for the advices about the power management IC's. I will take a look!

 

Luis

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