09-14-2018 10:30 AM
I need some help on the Zynq-7000 Bootrom error code. I have RSA AUTH enable on our Zynq7015 Silicon Rev3.1 board, and I am getting a 0xE00C Bootrom error code when I read the Slrc.RebootStatus register. However, I couldn't find that error code listed in the UG585 TRM and table 6-20. Could someone help with decoding the error code?
09-17-2018 02:10 PM
The error code 0xE00C is 0x200C plus bits 14 and 15.
0x200C = QSPI boot mode unable to find a valid header
bits 14 and 15 set = BOOTGEN_SIGNATURE_ERROR -- probably improperly created boot.bin - or large QSPI and not following AR57900
09-23-2018 07:07 PM - edited 09-23-2018 07:09 PM
Hi，we designed a board with ZYNQ 7z020 and S25FL256SAGNFI001(QSPI) ，the QSPI interface is 3.3V。In the online debugging mode, the board peforms good.When Program Flash with SDK ，I checked “Blank check after erase” and “verify after flash”，the reports the programing process is successful, as follows: Verify Operation successful. Flash Operation Successful
But ,when re-power on the board, it boots failed ,inclue ARM and FPGA。 And when read 0xF800_0258，the slcr.REBOOT_STATUS，the value was 0x0058600c。Refer to the datasheet，58 means bits 22、20 and 19 were set 1。
I think POR should be the last reset，but why DEBUG Reset and slc soft reset were also set 1?How should I check it?
Otherwise,bits[15:0] is BOOTROM error code,from your last reply， I know value 0x600C is 0x200C plus bits 14。BUT I do not understand the solution：
And why does bit 14 set 1？
How can I fix the issus?Look forward to your reply.
09-24-2018 06:29 AM
bit 14 indicates FSBL_PPK_FAILURE_ERROR. Are you using Authentication? If not, look at AR65240 and ensure your power-up and power-down is correct.
09-25-2018 01:58 AM
09-25-2018 05:27 AM
Look here AR68656