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shrsmas0
Visitor
Visitor
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Registered: ‎09-06-2018

Zynq7000 Dual-stacked QSPI Programming Failed with Image Size > 0x1740000

I have a Zynq 7000 (XQ7Z045RF900-1Q) board with x4 dual-stacked configuration QSPI (dual S25FL512S, 512MBit each). I can program the QSPI successfully with any image that is less than 0x1740000 bytes in size. For image size larger than that, the Vitis always reports that the verification failed at 0x740000. 

I used a logic analyzer to captured the verification read data at 0x740000 and found that the read data are actually from 0x1740000 in the .bin image file. The transactions captured by the logic analyzer when programing around 0x1740000 don’t show abnormity. The transitions are the same as that writing to other addresses and the bank register write (command 0x17, for setting address bit 25) is correct. However, I noticed that starting at 0x1740000, the wirte-in-progress time reported by the flash increases significantly, as shown below:

dual_stacked.png

I don't see any traffic on the 2nd QSPI when writing an image file less than 32MB. 

Thanks,

Max

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shrsmas0
Visitor
Visitor
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Registered: ‎09-06-2018

The Vivado/Vitis version is 2020.2

I also replaced the 512Mbit S25FL512S flash chips with 1024Mbit MT25QL01GBBB8ESF, and the issue was the same.

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abommera
Xilinx Employee
Xilinx Employee
60 Views
Registered: ‎10-12-2018

Hi @shrsmas0,

>> Can you share your flash programming log? Are you trying with 2020.2 mini u-boot? If yes, can you please try with 2019.2 mini u-boot?

>> Can you try run a flash polled example with test address above 0x1740000 to ensure there are no issues with hardware design?

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/qspips/examples

Thanks & Regards
Anil B
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