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phil.d.dawson
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Registered: ‎09-14-2018

ZynqMP u-boot fpga load commands (programming PL from u-boot)

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Hi,

I'm working on a PetaLinux build for a custom board (xczu5cg based) and am trying to understand how to program the FPGA from within u-boot.

Overview:

  • xczu5cg based board
  • Vivado/PetaLinux 2018.3
  • QSPI boot
  • PetaLinux build flow

Details:

If I build PetaLinux and pacakge BOOT.BIN to include the FPGA:

petalinux-package --boot --pmufw pmufw.elf --fpga system.bit --fsbl zynqmp_fsbl.elf --u-boot u-boot.elf --atf bl31.elf --force

Then the FSBL programs the PL correctly and everything works.

In u-boot i can run the "fpga info 0" command to get information about the fpga and "fpga loadb 0 <addr> <size>" to prgram the fpga using the system.bit bitstream that our build produces.

ZynqMP> fpga info 0
Xilinx Device
Descriptor @ 0x000000007feaa9e8
Family:         ZynqMP PL
Interface type: csu_dma configuration interface (ZynqMP)
Device Size:    1 bytes
Cookie:         0x0 (0)
Device name:    zu5cg
Device Function Table @ 0x000000007fe8c928
PCAP status     0xa0002fde

 

If instead i do not package the FPGA bitstream into BOOT.BIN:

 petalinux-package --boot --pmufw pmufw.elf --fsbl zynqmp_fsbl.elf --u-boot u-boot.elf --atf bl31.elf --force

So that I can leave the FPGA programming to u-boot, then the "fpga info 0" command doesn't recognize the Device Name and the "fpga loadb 0 <addr> <size>" command fails:

ZynqMP> fpga info 0
Xilinx Device
Descriptor @ 0x000000007feaa928
Family:         ZynqMP PL
Interface type: csu_dma configuration interface (ZynqMP)
Device Size:    1 bytes
Cookie:         0x0 (0)
Device name:    unknown
Device Function Table @ 0x000000007fe8c878
PCAP status     0xa02

ZynqMP> fpga loadb 0 $netstart $filesize
design filename = "Top;UserID=0XFFFFFFFF;Version=2018.3"
fpga_loadbitstream: Wrong bitstream ID for this device
fpga_loadbitstream: Bitstream ID xczu5cg-fbvb900-1-e, current device ID 0/unknown
fpga - loadable FPGA image support

 

If I use "bootgen" to convert the .bit to a .bin:

(bitstream.bif)

all:
{
        [destination_device = pl] system.bit
}
bootgen -image bitstream.bif -arch zynqmp -o ./system.bin -w

Then I can program the PL with this using:

fpga load 0 <addr> <size>

Questions:

  1. Why can I not program the PL with a bit file from u-boot if the FPGHA is not programmed from the FSBL?
    • The Solution+ZynqMP+PL+Programming confluence page says: From 2018.3 release onwards FPGA Manager supports loading of vivado and bootgen generated Bitstream and Bin files vivadobootgen[1]
  2. Why is the Device name unknown if the FPGA is not programmed by the FSBL?
  3. Is there any downside to using "fpga load" to program from a .bin vs "fpag loadb" from a .bit? (in particular we may need encryption/authentication later)
  4. Have a missed a resource (see references below) that explains this all a bit more clearly?

References:

I've used the following pages to try to understand how to program the PL from u-boot, but haven't managed to find the answers I'm looking for in them as most of the confluence pages focus on progrmaming the PL from Linux.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841847/Solution+ZynqMP+PL+Programming

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/124682257/U-Boot+FPGA+Driver

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842056/FPGA+Manager+ZCU102

 

Best Regards,

Phil

 

 

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Accepted Solutions
denist
Xilinx Employee
Xilinx Employee
1,480 Views
Registered: ‎10-11-2011

Converting the .bit to .bin using bootgen is the way to go especially if you are going to add security later on.

The .bin has an extra header at the beginning with a lot of secure information required to properly load the PL.

Is "fpga load" working for you if the FSBL is not previously run the bitstream?

 

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2 Replies
denist
Xilinx Employee
Xilinx Employee
1,481 Views
Registered: ‎10-11-2011

Converting the .bit to .bin using bootgen is the way to go especially if you are going to add security later on.

The .bin has an extra header at the beginning with a lot of secure information required to properly load the PL.

Is "fpga load" working for you if the FSBL is not previously run the bitstream?

 

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Don’t forget to reply, kudo, and accept as solution.
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phil.d.dawson
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Registered: ‎09-14-2018
Hi denist, Yes "fpga load" seems to be working for us if the FSBL is not loading the bitstream. If it is the way to go for security as well then we will use that as the solution. Is there a way of telling if the FPGA has successfully loaded from u-boot? Thanks, Phil
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