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x_abacadaba
Observer
Observer
191 Views
Registered: ‎12-21-2017

Zynqmp PLLs in ERROR_STATUS_2 always report PLL LOCK erors

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I've modified the pmufw to copy the PMU GLOBAL ERROR STATUS 1 and PMU GLOBAL ERROR STATUS 2 registers into 2 of the PGGS registers via a custom handler so that I can read them at boot and through soft reset errors.  I've noticed that every single PLL indicates lock errors on every boot:
https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
bits 12:8 are always set.  If I clear them, then issue a soft reset, they get set again.

x_abacadaba_0-1618591581846.png

Is this normal?  I think its odd because in order for the pmufw code portion to run (not the ROM portion), it must be pulled out of the QSPI.  But the QSPI requires the PLL in order to work properly.

I read this AR:
https://www.xilinx.com/support/answers/70168.html

Which seems to indicate that not al PLLs should have a LOCK error.  Maybe it is just normal at boot and I simply need to clear them at the end of the FSBL so that I can detect runtime PLL lock errors?

The reason for all of this testing is because I'm using a multiboot configuration, and very rarely, but repeatably, the system auto-boots into an alternate image without it being requested, so I'm attempting to gather information on what specifically caused the issue.
Thanks

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denist
Xilinx Employee
Xilinx Employee
154 Views
Registered: ‎10-11-2011

I think it's expected that the PLL will unlock during FSBL execution (psu_init.c) because the FSBL configures different dividers compare to bootROM.

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denist
Xilinx Employee
Xilinx Employee
155 Views
Registered: ‎10-11-2011

I think it's expected that the PLL will unlock during FSBL execution (psu_init.c) because the FSBL configures different dividers compare to bootROM.

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