02-12-2020 05:25 PM
zynq without DDR and boot with QSPI FLASH. The vivado version is 2018.3.
I modified the project based on the project of xilinx:
While all of them done, we get the informaion from uart as picture.
The follow information repeat again and again:
XILINX First Stage Boot Loader
Realease 2017.3 Feb 12
Pls tell us the possible reason for this?
02-21-2020 10:10 AM
The FSBL is aborting and jumping back to the vector table and restarting.
You must double check the changes you made. Maybe overwriting wrong memory?