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nixiebunny
Contributor
Contributor
347 Views
Registered: ‎01-26-2009

16 SSR FFT maximum clock rate

I'm hoping to build a broadband FFT spectrometer using the ZCU111. I need an FFT that will run at 250 MHz, and has 16 SSR paths.

I loaded the example 1D SSR FFT in Vitis_Examples/dsp/ and synthesized it. The result was that a 4x SSR FFT will run (more or less) at 250 MHz, but when I change the width to 16 SSR, then the speed drops to 80 MHz.

Is this the best that I can hope for?

Is the System Generator SSR FFT capable of 16 SSR at 250 MHz?

 

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vkanchan
Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎09-18-2018

Hi @nixiebunny ,

Sysgen SSR FFT can be used here. This uses HDL internally and should have higher performance than the HLS based design.

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nixiebunny
Contributor
Contributor
139 Views
Registered: ‎01-26-2009

Thanks for your reply. I figured that out and switched to the System Generator FFT. This brings up my next question, which I asked a few weeks ago.

Can you folks at Xilinx please work on the Vector FFT in system Generator to make it be a fully functional IP block, instead of a quick test unit with no features as found in the non-vector FFT?

 

 

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