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ryan2263132
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Registered: ‎03-20-2019

21DR sd_fec delay anormal

while employing our 5G data chain by using 5G LDPC decoder of sd_fec (see pg256-sdfec-integrated-block.pdf), we observe that some anormal delay of LDPC decoder cores appeared in our circuit. for example, a CB size 26112 bytes(bg=0 Zc=384) into a LDPC core, normal delay is about 30 us, but if we continue giving CBs in for a while, the delay can be >1000us.

some advises(set-up details or using tips)?  

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nathanx
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Registered: ‎08-01-2007

For each data block, a single input is required on the control (CTRL) input stream, specifying key
block specific parameters, such as block size. One control word (transaction) is required for each
data block, and data input stalls until the relevant control word is available. Did you send the control word before putting data into the core?

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