05-13-2018 06:12 AM - edited 05-13-2018 08:47 AM
I have read the almost all posts about the 2D FFT by using the Xilinx 1D-FFT IP core. The algorithm is obvious ; firstly take 1D-FFT of each serialy coming line in the image and then write the result into the BRAM through Port A by a BRAM Memory Controller. After that, the the line FFT result is read back from BRAM by skipping the address at a certain amount through Port B. (Thus you obtained the columns of the image). My question is that should I use one extra BRAM Memory Controller for read purpose only? Or using only one BRAM Memory Controller (in dual mode) is much more feasible than using two different BRAM Memory Controller (one is for write purpose only, and the other read purpose only) ?
05-13-2018 06:28 AM
Can you actually store all of this in BRAM? Say each row FFT is 1000 32-bit elements, and you want to store 1000 rows. That'll require 1000 32K BRAMs, which is going to be a problem on most chips.
05-13-2018 09:10 AM - edited 05-13-2018 09:22 AM
*Why do I try to take 2D FFT of a 1000x1000 image using one of Xilinx chips with small BRAM ?
*Probably I can take 256x256 or 128x128 portion of the entire image to handle this 2D-FFT task. i.e : Assume an 256x256 portion of the image and one pixel is 2Byte. 1D-FFT result for one pixel is; 2Bytes for real and 2Bytes for imaginary part as totaly 4Bytes. Then, necessary memory for 1D-FFT result of a line is 256x4Bytes = 1024Bytes. For 256 lines ; 1024Bytesx256 = 2Mbit BRAM is enough for 2D-FFT of an 256x256 image. At least xc7z015 or xc7z020 is needed for this task.
*I wonder that should I use two different BRAM Memory Controller (one for only write and one for only read purpose) for one BRAM memory? Because it is written like that in this post (Post)