06-21-2018 10:09 PM
I have designed 16 channel receiver using FIR.
Design constraints from LEFT to RIGHT are as follows :-
1. Clocking wizard :- 20 MHz,160 MHz,320 MHz.
2. System reset logic
3. 8 channel DDS with 8 different frequencies ( sine and cosine)
4. splitters :- for separating sine and cosine waves from dds
5. Multiplier :- A input => sinc pulse created using block memory generator
B input => outputs from splitters ( sine or cosine)
6. mux :- for clubbing these signals
8. DEMUX :- for separating these signals
9. ILA :- observing output on hardware platform.
dds :- 160 MHz
binary counter,reset logic, multiplier, block memory generator :- 20 MHz
FIR, DMUX, 4 bit binary counter :- 320
From the above configurations, I am getting perfect output in simulation as well as on ILA. But only issue is the TIMING ERROR that i am getting, which is not avoidable when i am using this design for practical applications.
Can you please tell me why i am getting this error ?
06-22-2018 04:31 AM
You need to include the section of the timing report that shows what paths the errors are on. Without that, we can't help, but if I were to make a guess, the problem would be in the demux. An 8 or 16 channel asynchronous demux at 320 MHz is tough in a 7 series.
06-25-2018 09:48 PM
I want to make separate IP for the modules that i have created and locked ips ( combine RTL modules and ips into sigle IP) in order to make design optimized. IS it possible sir?
According to my learning and reading from internet, it is not possible. Is there any solution to make design optimized ?