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Visitor
Visitor
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Registered: ‎07-23-2018

About the co-simulation issue in system generator

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Dear Everyone,

  Now I am trying to co-simulate my FPGA design in form of BLACK BOX in system generator(the module is write in verilog), the model output of FPGA Black BOX is connected to drive  a H-Bridge electrical circuit ( a switch-mode power amplifier), my problem is that the FPGA clock period is 10ns and the Simulink system period is 1 sec(that is the normalized period), but the electrical circuit connect with it works in a real time, that means it could not work in such normalized time, could anyone give any idea to deal with this? 

thanks a lot!

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Moderator
Moderator
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Registered: ‎08-01-2007

回复: About the co-simulation issue in system generator

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can you clarify your question? You can set Simulink system period to any value.

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Moderator
Moderator
921 Views
Registered: ‎08-01-2007

回复: About the co-simulation issue in system generator

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can you clarify your question? You can set Simulink system period to any value.

View solution in original post

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Visitor
Visitor
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Registered: ‎07-23-2018

回复: About the co-simulation issue in system generator

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Thank you, Moderator, it has been solved, i set the simulink system period in the Xilinx Token to 10ns(ie, 1e-8) to make it equal to the FPGA period clock, and then it works, the time in simulink now equals to physical time,  so the electrical circuit could then co-works.

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