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Visitor
Visitor
9,728 Views
Registered: ‎03-04-2008

An strange error when generate the DDR pcore to VSK_Diagnostics_91 example.

Hi all,
 
I would like to generate DDR pcore in VSK_Diagnostics_91 example.
But an strange error occurs:
========
A summary of Sysgen errors has been written to vsk_ddr_11_sysgen_error.log
Reported by:
  'vsk_ddr_11/ddr_edk/Delay1'
========
 
The vop and vio pcore can be generate and work.
Do I need other configure?
BTW, anyone have an example introducing how to use this pcore?
Thanks very much.
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Xilinx Employee
Xilinx Employee
9,718 Views
Registered: ‎08-07-2007

There is an example EDK project that should use the SysGen model you're referring to.

It's hard to say what went wrong since there wasn't an Error message listed.  Is there any further detail in the log file mentinoed?
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Visitor
Visitor
9,707 Views
Registered: ‎03-04-2008

Hi jeffreyh,
 
Can you generate the pcore?
The same situation happen when I get help from Xilinx support here, and they are wondering.
I think it is a version problem, as the log file just mentions the error occured from java engine.
I am using the matlab2007a, sysgen9.2, ise9.2, edk9.2.
 
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Visitor
Visitor
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Registered: ‎03-04-2008

This is the error log file:
 
--------------------------------- Version Log ----------------------------------
Version                                 Path
System Generator 9.2.01.1028            C:/Xilinx/dsptools/9.2.01.1028/sysgen
AccelDSP 9.2.01.1028                    C:/Xilinx/dsptools/9.2.01.1028/AccelDSP
Matlab 7.4.0.287 (R2007a)               C:/Program Files/MATLAB/R2007a
ISE 9.2.04i                             C:/Xilinx/ISE92
ISE 9.2i IP Update 1                    C:/Xilinx/ISE92
ISE 9.2i IP Update 2                    C:/Xilinx/ISE92
--------------------------------------------------------------------------------
Summary of Errors:
Error 0001: caught standard exception
     Block: Unspecified
--------------------------------------------------------------------------------
Error 0001:
Reported by:
  Unspecified
Details:
standard exception: XNetlistEngine:
An exception was raised:
java.lang.ClassCastException: com.xilinx.sysgen.netlist.ConstNet
--------------------------------------------------------------------------------
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Visitor
Visitor
9,695 Views
Registered: ‎02-14-2008

It is said that this pcore can be generated with matlab2006b, sysgen9.1i, edk9.1, ise9.1.
Where I get this old version tool?
Or is there an example for 9.2? How can I convert this example from 9.1 to 9.2? 
Thanks.
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Xilinx Employee
Xilinx Employee
9,682 Views
Registered: ‎08-07-2007

The design files for the VSK are "frozen" at 9.1 and are not supported on newer versions.  THis is because there were significant changes to the EDK 9.2 tools that do not allow them to be updated without a rewrite.

Your kit should have come with a CD containing the latest version of the tools supported by the VSK. 
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