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Contributor
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Registered: ‎01-27-2016

Behavioral simulation results different in different simulations

I am designing a continuously variable interpolation filter bank which is composed of a block that handles the non-integer portion of the interpolation and another block that implements a four stage halfband filter bank to cover integer interpolation rates from 2-16x.

The issue I am seeing when I run a behavioral simulation of the top level of the design and the halfband filter bank portion of the design by itself is that the simulation results are different for the halfband filter bank, even though the code used is identical.

I have seen an issue in the past where the source files do not always get updated when running a new simulation, however I make sure that I reset the simulation before I run if I have changed any files. 

Any ideas of the possible source of the issue? It makes it very difficult to make any progress in debugging my design since the simulation results are unreliable. Thanks.

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Contributor
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Registered: ‎01-27-2016

I found that by deleting the xsim.dir directory in the behavioral simulation directory that I am now getting the results I expect.

Any possibility that Xilinx will fix this issue in the near future so I do not have to manually delete the directory after every simulation?

 

Bill

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