Behavioral simulation with Coregen's FIR Compiler v3.2
I am trying to run a simulation in modelsim of a FIR generated with Coregen FIR Compiler v3.2 just to make sure I know how to apply the inputs and see the outputs toggling appropriately. At this point I don't care what kind of data I'm sending into it, just that I see the output controls toggling and some data coming out of it. I've run this thing for about 1ms and I see no data or control outputs toggling at all. The latency was calculated by the FIR Compiler to be around 356 clock cycles based on the # of taps(47) and it being a 3 channel FIR. My clock period is 2.667 ns(375MHz). There should be something coming out by 1ms. I've simulated the basic cores before, like RAM, FIFO's, multipliers, etc and I've had no problems. I'm just wondering if there is something basic I'm missing here. I made sure to include the .mif files in the modelsim work directory like I always do. The only thing that seems weird is that in the vhdl file that is generated by Corgen's FIR Compiler, there is no reference to the .mif file that is storing the coefficients. For RAM's that I've generated with Coregen before, there is always a reference to the .mif file(s) in the generated .vhd file. But even so, if there was no .mif file the coefficients would be zero(I assume, but that is a big assumption) and the output would be 0. But I should still expect the behavior model to generate the control outputs(RDY and chan_out). But they are not even toggling.
If someone has any ideas of what I'm doing wrong, I would really appreciate it.
If you generate a structural simulation model or run a post-translate simulation, you will not have to deal with a .mif file. The simulation will be slower but it would not use the behavioral model for the core (which requires a .mif). You could do this to verify that your coefficients are correctly embedded in the simulation file.
In customizing the core, you can also specify an RFD (ready for data) output. I would do this to make sure that your core is operating correctly and that your are inputting the expected sample during the assertion of RFD. If you throw an impulse as the filter when RFD is high, you will get the impulse response out of the filter.
Thanks for the quick reply. I did include the RFD output when I generated the core and was using that to make sure I only asserted ND and a new data sample when RFD was high. So I'm pretty sure I am operating the inputs correctly based on the FIR Compiler's documentation.
I've never run a post translate simulation before. If someone has done this before, can they take me through the steps or point me to some documention on how to do that.
http://www.xilinx.com/support/answers/8065.htm shows how to generate a post-translate simulation model via command line.
Within ISE, if you click on your top level in the sources pane, then go to the processes pane: implement design -> translate -> and double click on generate post-translate simulation model, then go into your project directory /netgen/translate you will find the post-translate simulation model there.
Of course the first thing you would want to check is that you have recompiled your simulation libraries after updating your service pack or IP update. Start -> Xilinx -> Accessories -> Simulation Library Compilation Wiz.
I was able to get a simulation to run with a post-translate netlist and I'm getting data out. However, I have another problem that I can't seem to figure out. I can only run this core at 200MHz. This is a virtex-5 part and based on the fir_compiler v3.2 documentation I should be able to run this around 400MHz or so. Anything above 222MHz exactly and it stops working. I do have ISE service pack 4 and I did recompile the simulation libraries using the Simulation Library Complilation wizard. So I'm not sure what I'm doing wrong at the moment. If anyone has any ideas I would really appreciate it.