12-11-2017 05:37 AM
I want to implement some arithmetic operations as shown below using VHDL/verilog.
res = a + b + c
d = a* b* c
f = d / e
Which is the best way to implement (optimized interms of power/resource) above expressions in VIVADO tool?
Can I use Xilinx adder / multiplirer / divider IP cores OR
Direct usage of expressions as shown below enough ?
res <= a + b + c;
d <= a* b* c;
f <= d / e;
12-11-2017 08:14 AM
Is vague. Power/resources is still vague. Just try it both ways. Examine the results. See what is done.
12-11-2017 10:45 AM
12-12-2017 04:38 AM
You probably need to use a core for division. f = d/e is generally not synthesizable. You may be able to write RTL to perform division but you are very unlikely to do any better than the core.
The rest of this post is mostly personal opinion. If you write your adder, subractor code in VHDL or Verilog, the synthesis tool will generally use fabric for this. The synthesis tool and the fast carry resources make this a good option. The core may give you explicit options for using a DSP slice but you can do this with an attribute if you take the time to look up the syntax. Writing the adder/subtractor in RTL does make the code more portable.
The synthesizer will almost always put a multiplication in a DSP slice if you write RTL and have a DSP available. A nice thing about the core GUI is that it will remind you that you need a couple pipeline delays for the DSP slice to work at a reasonable frequency. The synthesis tool is generally good enough to use the DSP registers if they are present in your RTL. So if you have enough experience to put enough registers before and after the multiplication and want portable code, write RTL. If you're just getting started, the multiplication core will help keep you on the right track.