12-05-2019 07:28 AM - edited 12-05-2019 07:29 AM
I would like to make a System Generator subsystem model that would permit the user to change the number of instantiated blocks like a generate statement in vhdl. I am trying to make a subsystem block with a small memory for each lane of a super sample data bus. I want to be able to scale it with the super sample parameter (ie. SSR=4 make 4 parallel memories, SSR=6 would make 6 parallel memories, SSR=8 would make 8 parallel memories).
An example of the type of model I would like to make is the Vector Complex Multiplier which can be found in the Xililnx SSR Blockset. When the SSR parameter of the model is changed, the number of lower level multiplier instantiations is change to the value of the SSR.
Any help would be appreciated.
12-09-2019 05:24 AM
Thanks for the reply, I have looked in UG897. It does not describe the solution I am looking for. The closest description is that of a library model, but it requires building individual subsystems if you want multiple operations from the same model.