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Mentor
Mentor
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Registered: ‎10-07-2011

CIC Compiler

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Hello all,

Using 2018.2 on Win10x64. I used the CIC Compiler to generate a decimation (downsampling) module.

  • FPGA Clock: 150MHz
  • Input Sample Rate: 15MHz
  • Downsampling Factor: 100 (150kHz output sample rate)
  • 3 stages

I used Matlab to generate testbench data and for some reason, Matlab and FPGA data don't match at all.

Did anyone ever succeeded in using Matlab to model the CIC IP? If so, any hint?

Thanks!

Claude

 

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Mentor
Mentor
342 Views
Registered: ‎10-07-2011

It appears most of the mismatch is due to different gain factors between Matlab and the CIC Compiler IP. In my case, the mismatch is approximately a factor of 16 (or 15.871). There is also a slight offset.

At the end, the IP is working OK. At least, I can use it...

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Highlighted
Mentor
Mentor
343 Views
Registered: ‎10-07-2011

It appears most of the mismatch is due to different gain factors between Matlab and the CIC Compiler IP. In my case, the mismatch is approximately a factor of 16 (or 15.871). There is also a slight offset.

At the end, the IP is working OK. At least, I can use it...

View solution in original post

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Registered: ‎06-21-2017

Two things about the gain.  Unless the decimation factor is a power of two, a hardware implementation of a CIC filter will not have unity gain.  The other thing to remember is that if you are using Vivado, the CIC will have an AXIS output and will pad the output to an integer number of bytes. 

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