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Registered: ‎07-08-2010

CORDIC v4 Translate Function Issue



I'm trying to implement a cartesian->polar conversion using the CORDIC v4 IP core. Set up is as follows:


Translate function

Parallel architecture

Maximum pipelining

Phase output in scaled radians

16 bit wide input and output, both registered

Truncate rounding mode

Coarse rotation

Embedded multiplier compensation (have also tried no compensation)


I have set up a test board to feed a set of 8 switches into the most significant 8 bits of the X and Y input values. The 8 switches are fed to both the X and Y value, so both X and Y are the SAME value and are kept positive by simply not using the first two switches. It seems to me that this should give me a constant phase output (or close to constant) regardless of switch inputs, while changing magnitude output. The phase output changes significantly with different switch configurations and the magnitude output isn't what I expect it to be. I have reviewed the CORDIC datasheet and read through the input and output formats. I am pretty certain that I am interpreting the data properly.


Does anyone have any experience with this? The code is very simple:


-- Component struct
component cordic_v4_0
    clk        : in std_logic;
    nd         : in std_logic;
    phase_out  : in std_logic_vector(15 downto 0);
    x_in       : in std_logic_vector(15 downto 0);
    x_out      : out std_logic_vector(15 downto 0);
    y_in       : in std_logic_vector(15 downto 0)
end component;

signal cordic_Xin, cordic_Yin   : std_logic_vector(15 downto 0); -- cartesian inputs
signal cordic_R, cordic_THETA   : std_logic_vector(15 downto 0); -- polar outputs
signal cordic_nd                : std_logic;


-- Instantiation
    U_car2pol : cordic_v4_0
      Port Map (CLK_BRD, cordic_nd, cordic_THETA, cordic_Xin, cordic_R, cordic_Yin);

    cordic_nd <= '1';
    process(CLK_BRD, SW_RESET)
        if SW_RESET = '0' then
           LED_R <= x"00";
           LED_B <= x"00";
           cordic_Xin <= x"0000";
           cordic_Yin <= x"0000";
        elsif rising_edge(CLK_BRD) then
           LED_R <= cordic_THETA(15 downto 8);
           LED_B <= cordic_R(15 downto 8);
           cordic_Xin <= (not SW) & x"00";
           cordic_Yin <= (not SW) & x"00";
        end if;
    end process;

 LED_R and LED_B are led arrays that I am monitoring the results on. CLK_BRD is a 50MHz global clock.


I have also tried the examples from the datasheet, and I don't get the same results. I've looked through the answer database and through this forum and haven't found anything. Hopefully I'm missing something obvious!


Thanks in advance!

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1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎08-16-2007

You might want to consider opening a Webcase if you don't get any responses as this sounds like maybe a misunderstanding in interpreting the results or a setup problem if you're are not seeing the same results as the examples.

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