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prdorrell
Adventurer
Adventurer
826 Views
Registered: ‎03-05-2008

Can I control output sampling rate of a System Generator core by controlling input ce_1?

Dear Forum,

 

I have a System Generator design that generates a test pattern at a fixed division of the input clock. I now want to slow the output rate without changing and regenerating the model. The document user guide UG897 says (p53):

 

 "... ce_1 must be tied high ..."

 

... but I take this as being part of an example, rather than general guidance, otherwise what would be the point of having it if it's always tied high !?

 

I'm hoping that instead of tying ce_1 high I can pace it, e.g. high every other clock to simply halve the rate. My question is: will this work? ... and what about the derived clock enables ... will these be in the correct ratio to my new ce_1 ?

 

Kind regards

Paul

 

 

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2 Replies
jmcclusk
Mentor
Mentor
819 Views
Registered: ‎02-24-2014

If you have propagated the clock enable correctly through your design, it should work.    It's easy enough to test by enabling your clock enable 50% (or 10%) of the time, and watching your output data flow.   

Don't forget to close a thread when possible by accepting a post as a solution.
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prdorrell
Adventurer
Adventurer
762 Views
Registered: ‎03-05-2008

Thank you jmcclusk for your reply. Your empirical "try it and see" approach is good advice ... I'd never trust any of my assumptions without testing! However, I'm still hoping for a more general response from those who make the System Generator tool, specifically about the line in their documentation:

 

 "... ce_1 must be tied high ..."

 

Xilinx guys, can you set me straight on this issue please?

 

Kind regards

Paul

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