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Explorer
Explorer
3,008 Views
Registered: ‎11-02-2011

Can SysGen support incremental compilation?

Hi all,

 

  I have a SysGen project. Sometimes, there is only a little bit that I should change for the design. But I must regenerate HDL netlist. You know it will cost me a lot of time . Can SysGen support incremental compliation or it will support this feature in future?

 

Thanks.

Best Regards. 

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Xilinx Employee
Xilinx Employee
3,004 Views
Registered: ‎08-01-2007

Re: Can SysGen support incremental compilation?

SysGen does not support incremental compilation.

This may change in the future.

Chris
Video Design Hub | Embedded SW Support

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546 Views
Registered: ‎03-18-2014

Re: Can SysGen support incremental compilation?

Is it future yet?

 

OOC, CC, Cache, _netlist_sim... Does Xilinx have an example project, where there are Xilinx IPs, 3rd party IPs, BD IPs, sysgen IPs, custom IPs IPs from other projects are used in the form  of OOC, cached and DCP and both minimum synthesis and maximum change detection is achieved? IP process is ruining such a good Xilinx tool Vivado.

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