03-15-2012 11:54 PM
I have a SysGen project. Sometimes, there is only a little bit that I should change for the design. But I must regenerate HDL netlist. You know it will cost me a lot of time . Can SysGen support incremental compliation or it will support this feature in future?
03-16-2012 09:00 AM
SysGen does not support incremental compilation.
This may change in the future.
05-10-2018 12:39 PM
Is it future yet?
OOC, CC, Cache, _netlist_sim... Does Xilinx have an example project, where there are Xilinx IPs, 3rd party IPs, BD IPs, sysgen IPs, custom IPs IPs from other projects are used in the form of OOC, cached and DCP and both minimum synthesis and maximum change detection is achieved? IP process is ruining such a good Xilinx tool Vivado.