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wangxiaoliang
Observer
Observer
11,758 Views
Registered: ‎09-12-2008

Can we do the behavior simulation of FFT IP core in verilog?

Hello

The information of my project: ISE 10.1 ,modelsim 6.3C, FFT core 5.0

     When I generate the IP core in VHDL and make the instantiation in VHDL ,the simulation is right.

     But when I generate the IP core in verilog and make the instantiation in verilog, the modelsim shows that "# ** Error: fft_top.v(48): Module 'myfft' is not defined."

     Then I generate the IP core in VHDL and make the instantiation in verilog,when i make the synthesize,the error is "ERROR:HDLCompilers:87 - "fft_top.v" line 43 Could not find module/primitive 'myfft'"

    I don't know what's wrong with my project,and I attch my project here.Wish your help.Thank you very much.

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11 Replies
ywu
Xilinx Employee
Xilinx Employee
11,742 Views
Registered: ‎11-28-2007

Can you attach your project in zip format?

 

Cheers,

Jim

Cheers,
Jim
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wangxiaoliang
Observer
Observer
11,738 Views
Registered: ‎09-12-2008

Hello ,JIM:

       I attch my project in .zip format now.Wish your help.Thank you.

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ywu
Xilinx Employee
Xilinx Employee
11,735 Views
Registered: ‎11-28-2007

How do you compile the files in Modelsim? You probably need to compile my_fft.v before fft_top.v

 

Cheers,

Jim

 

 

Cheers,
Jim
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wangxiaoliang
Observer
Observer
11,727 Views
Registered: ‎09-12-2008

Hello jim,do you have QQ or msn ,I wish to talk with you about this problem , because the same I do in VHDL ,the result is perfact.

Would you please help me ,I have been trapped here for a long time......

And thank you very much.

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wangxiaoliang
Observer
Observer
11,710 Views
Registered: ‎09-12-2008

Hello ,jim:

There is no error when I compile these files.But how can I do the simulation?

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ywu
Xilinx Employee
Xilinx Employee
11,697 Views
Registered: ‎11-28-2007

Your zip file only has source files. How do you compile files? Do you use a script (do file in modelsim)? What exactly did you do before you get the error? How do you run simulation with VHDL files?

 

Cheers,

Jim

 

 

 

Cheers,
Jim
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wangxiaoliang
Observer
Observer
11,694 Views
Registered: ‎09-12-2008

Thank you for your attention at my problem.

At first,I use IP core generator to generate an IP core in version 5. Then  I make an initialization of it .At last I make an testbench for it.When I do it in VHDL,there is no problem,and the output is right.But when I do it in verilog,the error shows like what I say.

I attch the whole project here.Thank you for your checking.

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ywu
Xilinx Employee
Xilinx Employee
11,655 Views
Registered: ‎11-28-2007

Works for me. Make sure you select "Behaviroral Simulation" for "Sources for" then run "Simulate Behaviroral Model" in the "Processes" window (see screenshot below). If it still doesn't work, attach the file "transcript" in your project directory to the message.

 

Cheers,

Jim

 

Cheers,
Jim
ise_runsim.gif
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wangxiaoliang
Observer
Observer
11,651 Views
Registered: ‎09-12-2008

Hello,jim:

     That is so strange,hoho!The same thing I do today ,I see the wave!!

     But , I find another problem,the wave is wrong:

     First, the xn_index is zero....does that mean I don't put in the number?

     And there is no output?

     Maybe my fft_tb.v is not written correctly, but I think I should have the xn_index at least.

     I doubt that the core is not transferred.

     Would you please have a look at my fft_tb.v file?Thank you very much!!!

 

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wangxiaoliang
Observer
Observer
5,684 Views
Registered: ‎09-12-2008

Hello,jim:

      I am puzzled now.The project of fft4 can show the wave now,then I create a new project which named fft .It can not work now ,and the problem is the same.What else,I do nothing about fft4,it works .....why....I attch the project here ,and the script is in it. Wish your help. 

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wangxiaoliang
Observer
Observer
5,670 Views
Registered: ‎09-12-2008

Hello,Jim:

     Would you please send me an example of using FFT core? Wish your help....I am in the soup for these days.  I can't find the problem.  :( 

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