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282 Views
Registered: ‎07-10-2019

Change in data Path Options (rounding mode) of FIR compiler on conversion of simulink model to its equivalent vivado HDL netlist

Hi,

I am using Matlab R2015b (system generator 2015.4) for making xilinx simulink model using xilinx blockset and Vivado 2015.4 to run the converted netlist from simulink model on Artix-7 Evaluation board.

I am using FIR compilers in stages for digital upconvertion purpose. In simulink model I am keeping the "output Rounding mode" as "symmetic_Rounding_to_Infinity" for all 3 FIR's filters I am using in concatenation. But while converting this model to vivado netlist code all FIRs (except 1st) is changing its "output Rounding mode" as "Full Precision" and in drop button "symmetic_Rounding_to_Infinity" is not available and thus I am getting much higher output bits from each stage than desired.

Attached Snapshot of simulink model (with 25 bit, round to infinity) and its vivado generated code (with 38 bit, full precision).simulink_model.PNGfir_generated_in_vivado.PNG

Thanks 

Vikas

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Registered: ‎08-16-2018

Re: Change in data Path Options (rounding mode) of FIR compiler on conversion of simulink model to its equivalent vivado HDL netlist

Can you please share the complete design with us.
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Registered: ‎07-10-2019

Re: Change in data Path Options (rounding mode) of FIR compiler on conversion of simulink model to its equivalent vivado HDL netlist

Hi,

Thanks for the reply.

I tried to upload the project but site is not allowing to do it, so I have attached the snapshots of all the settings of sample project where 3 FIRs are concatenated.

I am following following steps to make Xilinx simulink model which is converted to HDL netlist:

Simulink Xilinx Block sets settings

fig_1.png

  • Fig_1

Token Settings

fig_2.png

  • Fig_2

Clocking:

FPGA clock period (ns):  5

Simulink system period (sec) : 1/204800000

Perform Timing analysis : None

 

General: Defaul

  • Sine Wave5
  • fig_3.png
  • Fig_3

Data types: single

  • Gateway In4
  • fig_4.png
  • Fig_4
  • fig_5.png
  • Fig_5

 

  • FIR Compiler 7.2.6
  • fig_6.png
  • Fig_6

 

Coefficient vector:

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0.0041596630099198818 0.0035811877093297547 0.0029965838780752307 0.0024073607623964618 0.0018149689909520343 0.0012209188807603035 0.00062655170084481083 3.3235671470660144e-05 -0.00055774025810256952 -0.0011449330149276044 -0.0017270708175365303 -0.0023029389812656131 -0.0028714865317015317 -0.0034313728244127497 -0.0039814671974416158 -0.0045207881687949663 -0.0050484934398038056 -0.0055631631597667479 -0.0060642917015569604 -0.0065509252080511397 -0.0070220388995004719 -0.0074772498898488336 -0.0079155417922435866 -0.0083365606091485803 -0.0087395495797471176 -0.0091241374284497141 -0.0094897402211704032 -0.00983603669942445 -0.010162580123177592 -0.010469143965654201 -0.010755433822799832 -0.011021357199400929 -0.011266755503975776 -0.011491637776643835 -0.011695922351096651 -0.011879664122158524 -0.012042852483167846 -0.012185666825782503 -0.012308263598911679 -0.012410983309787245 -0.012494057548751557 -0.012557812767630881 -0.012602440211331643 -0.012628359438209795 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fig_7.png

  • Fig_7
  • fig_8.png
  • Fig_8
  • fig_9.png
  • Fig_9
  • fig_10.png
  • Fig_10

 

  • FIR Compiler 7.2.7

 fig_11.png

  • Fig_11

Coefficient Vector:

[0.0013048955783505156 0.0015877547306928912 0.0025189211668869785 0.0037736613623847544 0.0054227648724232821 0.0075365663766492168 0.010193203005368979 0.013472562235095471 0.017455754058847743 0.022226297421752028 0.027862646255964612 0.034441516682663702 0.042030495817242469 0.050691154549291226 0.060471758285415997 0.071408704590259803 0.083520927538964104 0.096810773810427214 0.1112605516160087 0.126832323628255 0.14346593028061089 0.16107845043259525 0.17956439241488861 0.19879582494816067 0.21862409005521949 0.23888036724989206 0.25937834322191916 0.27991595242748735 0.30027917082474742 0.32024503919478675 0.33958572368366435 0.35807225221923311 0.37547855699957289 0.39158597841787329 0.40618720873441982 0.41909087708393078 0.43012476047656006 0.43913976655446463 0.44601241377754203 0.45064794682098408 0.45298194282813886 0.45298194282813886 0.45064794682098408 0.44601241377754203 0.43913976655446463 0.43012476047656006 0.41909087708393078 0.40618720873441982 0.39158597841787329 0.37547855699957289 0.35807225221923311 0.33958572368366435 0.32024503919478675 0.30027917082474742 0.27991595242748735 0.25937834322191916 0.23888036724989206 0.21862409005521949 0.19879582494816067 0.17956439241488861 0.16107845043259525 0.14346593028061089 0.126832323628255 0.1112605516160087 0.096810773810427214 0.083520927538964104 0.071408704590259803 0.060471758285415997 0.050691154549291226 0.042030495817242469 0.034441516682663702 0.027862646255964612 0.022226297421752028 0.017455754058847743 0.013472562235095471 0.010193203005368979 0.0075365663766492168 0.0054227648724232821 0.0037736613623847544 0.0025189211668869785 0.0015877547306928912 0.0013048955783505156]

fig_12.png

  • Fig_12
  • fig_13.png
  • Fig_13

Rest settings same as previous block.

  • FIR Compiler 7.2.8
  • fig_14.png
  • Fig_14

 

Coefficient Vector: [0.0068710599211463212 0.039768377091703222 0.12606088513805835 0.27945853811205307 0.47423619395217681 0.6427653544436539 0.70991182313200563 0.6427653544436539 0.47423619395217681 0.27945853811205307 0.12606088513805835 0.039768377091703222 0.0068710599211463212]

 fig_15.png

  • Fig_15
  • fig_16.png
  • Fig_16

Rest settings same as previous block.

Note: After model is completed, it is converted into Vivado Synthesizable HDL netlist where the “Output Rounding mode” and “Output width” is changing from the 2nd stage of FIR (1st stage is OK).

Regards

Vikas

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