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Registered: ‎01-15-2009

Changing the (Xilinx Blockset) RAM read address on the fly.

Hi all, I’m using System Generator (10.1) to implement an algorithm that performs overlapping before windowing and FFTing.  All the data to be processed will have already been collected before this algorithm executes. One approach I’ve considered is to store my data set in a Xilinx RAM block.  Then, between each iteration of the FFT, I would offset my read address by the overlap amount. The control logic to support this offset addressing (using elements from the Xilinx blockset, such as counters (to feed the address line), constants, registers, logical and relational blocks) seems to get torturous very quickly.  But perhaps my inexperience with the tools is part of the problem.  Has anyone tackled a similar problem?  If so, was it painful to solve?  Would it make more sense to forego control blocks and implement the logic in an M-Code block instead? There are several complications that I have omitted, but right now I’m focused on the offset addressing problem outline above.  Any help appreciated. Thanks everyone, LMC
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