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benlapointe
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Registered: ‎02-13-2009

Clocking Multipliers at a faster rate than the Logic around them

I have constructed a 4-Tap FIR Filter in System Generator. 

 

My issue is: I clock my data through the Filter at 32 MHz, but I would like to clock the Multipliers at a faster rate (at least 100 MHz).  The reason is: The Multipliers Blocks have a 3-cycle latency because they are pipelined.  The Filtered data is later processed with logic clocked at 250 MHz and used for signal detection.  This 3-cycle delay is holding me back because 3 cycles at 32 MHz equals 24 cycles at 250 MHz.

 

My question is: Is there any simple solution for getting the multipliers to give their result as fast as possible?  Is there any way to non-pipeline the multipliers?  Is that even recommended? 

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anirudhseth
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Registered: ‎03-25-2009

If you use the multiplier within the DSP elements then they can be clocked at frequencies upto 410 Mhz. You can use the DCM to generate the required clock ratio ( in your case clkx3 ), this clock will be synchronous to the system clock.
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