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Anonymous
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Co-simulation with Artix 7 device

Hi, I'm trying to get an Artix-7 device to operate in co-simulation mode.

 

A basic IO test (gatewayIn to GatewayOut) works fine and loads on the FPGA. However, when I try to connect the GatewayOut port to a pin (e.g. I set IO pad location to {'M16'} and IO standards to {'LVCMOS33'}  ).

 

Previously with Spartan-6 devices I would create a board file and install non-memory mapped ports and use these to connect directly to a pin. With the new version (2016.2) it seems the option has been removed, or at least I can't seem to find how to do that.

 

The error that I get is the following:

 

ERROR: [IP_Flow 19-3458] Validation failed for parameter 'AXI Address Width(C_AXI_ADDR_W)' for BD Cell 'hwcosim_cmd_proc'. Value '3' is out of the range (4,32)
INFO: [IP_Flow 19-3438] Customization errors found on 'hwcosim_cmd_proc'. Restoring to previous valid configuration.
ERROR: [BD 41-245] set_property error - Validation failed for parameter 'AXI Address Width(C_AXI_ADDR_W)' for BD Cell 'hwcosim_cmd_proc'. Value '3' is out of the range (4,32)
Customization errors found on 'hwcosim_cmd_proc'. Restoring to previous valid configuration.

 

I think it is not due to my board definition file since I get the same error if I try to generate using one of the Xilinx files.

 

Any help anyone can offer would be appreciated.

 

 

 

3 Replies
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: Co-simulation with Artix 7 device

change .prj file parameters manually

C_S_AXI_ID_WIDTH

check this ARs as well

https://www.xilinx.com/support/answers/60625.html
Thanks and Regards
Balkrishan
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Anonymous
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Re: Co-simulation with Artix 7 device

What file do you mean? My board definition files are all xml. Other than that I am using only Matlab at the moment.

 

I checked and the issue only occurs when I tick the box 'specify IOB location constraints'. It also happens regardless of whether it is a gateway in or out.

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Anonymous
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2,278 Views

Re: Co-simulation with Artix 7 device

Ok so I had another look at this today and found the same issue with an earlier version 2015.4.

 

In any case I found a workaround. Apparently if I add an extra gateway-out but with the interface set to AXI4-lite, then it is able to generate the hwcosim block without error.

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