First, on the mac.vhd file for lab 6. There are a few problems with the VHDL, compared to Xilinx recommendations.
1. Uses asynchronous active low reset. Recommend making it a synchronous active high reset.
2. Sensitivity lists have more signals than necessary in clocked processes. Depending on simulator sophistication, this can lead to slower than necessary simulations as any time an event on one of those unnecessary signals occurs, the process executes. (That is, unless the simulator has an optimization that effectively removes such unnecessary signals on sensitivity path). Even if simulator is not dragged down, the code example in mac.vhd could have unintended consequences with regard to engineers who are new to Xilinx/Vivavo/VHDL/SysGen.
Next, on the recommendations for black box labs (I have not reviewed all the labs):
1. It is in Xilinx's best interest to show more on the black box:
a. do a lab with two different data path inputs, with one output. There are some complications here for example with entity interface and .m file modifications, and such a simple example would speed up time to market for engineers to show a quick path through those complications.
b. Do an example with a flag output (non-DSP outout).
c. Do an example with a latency, and if and how the CE output must be generated.
Caveats: I have played around with SystemGenerator, but since I'm proficient at matlab (oldschool .m) and VHDL, I have not used SysGen on a real project other than to help other engineers who have sysgen projects, or for exploring algorithms using HWIL. So take my advice with a grain of salt, but it is given in good faith.
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