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7,079 Views
Registered: ‎02-10-2015

Cordic Pipeline Issue

Hi All

 I am currently trying to use the Cordic IP with maximum pipelining with parallel architecture for translate functionality. What I find is the ip takes in only alternate inputs if a new input is given to it on every clock cycle. That is in order for the IP to work correctly I need to give it one for two clocks and then give another input for another two clocks so I get the correct data every clock cycle after the intial latency is done. But the user manual says that it should give the output every clock cycle for a a continuous stream of inputs and that is how the pipelined architecture should work in general. So I am not sure if its a bug in the IP or is there something I am misssing.

 

 

I have attached two pictures. One in which phase out changes twice. in that picture the 2 input values are held for a total of 5 clocks. Another picture in which phase out changes only once. Here the inputs change every clock

 

Any help is appreciated

 

cordic_not_workin.PNG
cordic_WORKING.PNG
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3 Replies
Xilinx Employee
Xilinx Employee
7,051 Views
Registered: ‎08-02-2011

Re: Cordic Pipeline Issue

Try to keep sending in input values (i.e. assert nd) to flush the pipeline.
www.xilinx.com
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7,046 Views
Registered: ‎02-10-2015

Re: Cordic Pipeline Issue

Hi I have tried upto a 100 values but the IP just skips the second input all together but after that it seems to be working fine. I am not sure why is this happening. Also is it safe to assume that the IP will process all the inputs properly after the initial skipping.

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7,043 Views
Registered: ‎02-10-2015

Re: Cordic Pipeline Issue

expected phase is  -2336 actual is  -2351
expected phase is  -2350 actual is   5175
expected phase is   5176 actual is   6011
expected phase is   6012 actual is  -5969
expected phase is  -5968 actual is   -419
expected phase is   -418 actual is   -842
expected phase is   -842 actual is   -184
expected phase is   -184 actual is  -1811
expected phase is  -1810 actual is   2669
expected phase is   2670 actual is   1496
expected phase is   1496 actual is  -1082
expected phase is  -1082 actual is  -1216

In the above display if you see the first expected and actual phase match but then from second value they are one off due to the IP skipping the second input. This was taken from a testbench that sends upto a 100 input smaples continuously. That is nd is asserted and a new data goes in every clock.

 

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