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talitha
Observer
Observer
14,620 Views
Registered: ‎12-06-2007

DDC complex system generator

Hello,
 
I am trying to implement a circuit similar to the examples found for an DDC, though It is absolutely necessary to have a complex input signal for my mixing device. In Matlab I had done this with an NCO with complex exponentials. Though how in the world can I make this with Xilinx blocks with the System Generator. The dds block can  not achieve this for me.
 
Please help me
 
Talitha




Message Edited by talitha on 12-06-2007 07:09 AM
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9 Replies
jeffreyh
Xilinx Employee
Xilinx Employee
14,613 Views
Registered: ‎08-07-2007

Because System Generator represents hardware the real and imaginary portions of your signal must be represented as individual fixed point numbers.  Typically this is done by multiplying your input signal by both the SINE and COSINE output of the DDS to generate the real and imaginary components of your signal.

Xilinx has an application note covering a lot of details of how to create a DUC or DDC here:
http://www.xilinx.com/support/documentation/application_notes/xapp1018.pdf
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talitha
Observer
Observer
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Registered: ‎12-06-2007

Thanks for the reply,
 
I will read the document you linked, though I have tested the use of a SINE and COSINE coming out af a DDS. When using a complex signal from the NCO and plotting this in an FFT, gives me for example only a signal at 99MHz (fs=120MHz), Though how can I see this with the Sine and Cosine, if I now add them and plot them in and FF I get also the 21MHz signal which is undesired.
 
Talitha
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craigdekker
Visitor
Visitor
14,536 Views
Registered: ‎12-14-2007

jeffreyh,


From a Memec evaluation board with a Xilinx xc4fx12 chip I was able to generate a 10 Mhz signal with the Xilinx IP Core DDC V 1.0.  However when I move the same design (after updating the chip and DDC core gui) to a board that uses a Xilinx xc4fx100 chip the DDC now generates roughly a 4.x Mhz signal.  Changing the DDC gui to 25 Mhz produces a signal at just below 10 Mhz.

The board (Wild Star) with the xc4fx100 chip is made by a componay called Annapolis Micro Semi which does not allow direct use of the Xilinx ISE gui though does use xst and par and something else to generate an image.  After updating the ISE project to run on the xc4fx100 chip I load only  the vhd and ngc files into the equialent Wild Star project.

I generated a webcase for this though I was told that the DDC V 1.0 core was only tested on the VII chip.

Do you have any idea why DDC may be generating a signal roughly 2 to 2.5 times smaller in the xc4fx100 chip vs the dc4fx12 chip?

Hopefully I am doing something that is obviously wrong to someone has been doing this for a while because I have not seen anything like this in the literature and I am really wasting a lot of time trying to build a good filter around an ouput that I really can not control.

If there is no fix for this can you recommend another similar component?

Thank you,
Craig
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jeffreyh
Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

The important thing here when going between various hardware platforms is the system clock rate between each platform.  The rates are all relative to the system clock that drives the IP so if this changes then the IP needs to be regenerated.
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talitha
Observer
Observer
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Registered: ‎12-06-2007

Currently I have a working system, well at least in Simulink, with both simulink and system generator blocks. Though Since I want to implement this all in a Virtex 5 module I am bounded to use the DDS compiler v2.0. Unfortunately by using this DDS block I get an error. It says that the output is NaN, and I can not continue with this signal. Anyone familar with this error?


Attempt to convert a NaN...

Talitha
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jeffreyh
Xilinx Employee
Xilinx Employee
14,487 Views
Registered: ‎08-07-2007

Some blocks can accept a NaN or undetermined value as an input while others cannot. 

Take a look at answer record 23000 for some ideas on how to resolve any issues with NaNs.
http://www.xilinx.com/support/answers/23000.htm
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talitha
Observer
Observer
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Registered: ‎12-06-2007

The main question remains, how come does a DDS v4 does nog give this problem, though the DDS compliver V2, which is the only one that seems to be suitable for Virtex 5 does.
Further I have tried the given problem solvers, though none seems to solve it. The output of the DDS remains NaN and with this I can not continue in my design.

Using any of the solutions does not seem to solve the problem either, it keeps giving me error messages of NaN.

Talitha


Message Edited by talitha on 12-19-2007 02:40 AM
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jeffreyh
Xilinx Employee
Xilinx Employee
14,461 Views
Registered: ‎08-07-2007

Using a configurable subsystem with the "Indeterminate Probe" block will remove the NaN coming from the block and replace it with 0's.

Please open a support case for further help with this problem:
http://www.xilinx.com/support/clearexpress/websupport.htm
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anee_anil
Adventurer
Adventurer
8,044 Views
Registered: ‎01-16-2008

Hi,

 

I am facing the same problem.

 

Can you send your result to my mail ID   anil.haladipur@gmail.com 

 

Thanks in advance

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