05-03-2019 10:32 AM
I am currently working with the DDS Compiler 6.0 and have been noticing strange frequency offsets in simulation regardless of what frequency I use. Below attached is a zip of my configuration of the core (in this case I'm only looking at the 100 KHz signal to keep things simple).
For my simulation set up, I am using the encrypted library and am instantiating the VHDL core within my system verilog design file, which then is part of a cosimulation suite with Matlab. I have also attached the .tcl file I used for compiling the encrypted cores.
Within Matlab I wait for an extended amount of time (100 + clock cycles) before I start capturing the streaming data which I then view in freqz and an FFT plot which shows a frequency error from the NCO. The Freqz frequency and phase plot are also attached. For the record I capture about 44,000 contiguous samples before performing the FFT opertion.
As can be seen from the Freqz plot, the frequency is not set on 100 KHz but has a noticeable offset. Is this something that can only be found in simulation? Or is there something fundamentally wrong in my approach in designing with this core. If there is any additional information required, please let me know.
05-03-2019 10:41 AM
How many bits is your phase accumulator?
The resolution of a DDS is FCLK/2^n where n is the accumulator width. So, if you have 10 bit DDS, that is ~ 1/1000 (1/1024) of FCLK for a step. For some choices, the frequency is perfectly accurate, for others it has to be a step to the next integer divided result.
05-03-2019 10:46 AM
My phase accumulator width is 16 bits. However I configure it under the "System parameters" tool bar. In System parameters I have selected a frequency resolution of 1 Hz. In the Additional Summery tab the actual frequency for the 100KHz signal is 99.9999 KHz