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3,600 Views
Registered: ‎08-11-2016

DDS Compiler Fragmented Output

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Hello,

 

I've used the IP core generator to create a sine wave DDS generator. Input clock is 200MHz, output is 2 MHz, output width set to 14 bits, and phase width set to maximum. I have the core set to a constant phase increment. I am saving this sine wave in memory then reading out over serial. Although I do get a 2MHz tone, there is a fragment about every 5 microseconds (see attachment) - as if the internal phase jumps by a couple radians. Why does this happen? Is there any way to avoid this fragment?

figure_1.png
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6,066 Views
Registered: ‎08-11-2016

Issue turned out not to be with the DDS core at all. I had a bug in the memory which caused only the first 1024 samples to be accessible, so those 1024 samples were just repeating in the plot. 

 

Thanks for the help everyone!

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7 Replies
3,599 Views
Registered: ‎08-11-2016
Should note that the figure is only showing the first 8 of 14 bits.
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
clk should be free running and clean , can you share xco/xci file . are you using fixed mode or programmable
Thanks and Regards
Balkrishan
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3,578 Views
Registered: ‎08-11-2016

XCO file is attached. For clock, I am using an onboard crystal oscillator (50MHz) (see Mojo FPGA Development Board), and then PLL to generate 200MHz. For the DDS core, I am using fixed mode. 

 

Please let me know what you think the issue may be stemming from. Thanks in advance!

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Xilinx Employee
Xilinx Employee
3,537 Views
Registered: ‎08-02-2011

Hello,

Does "the figure is only showing the first 8 of 14 bits" mean the LSBs or MSBs?

www.xilinx.com
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3,468 Views
Registered: ‎08-11-2016

MSBs, I've simply dropped the least significant 6 bits. The problem persists if I generate a core that is just 8 bits to begin with as well. I've also tried slowing the clock down to 50MHz, and still get a clear fragment.

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3,461 Views
Registered: ‎08-11-2016

Made a simplified version of my project to recreate this problem, attached below. Can anyone recreate this?

This time I just used the 50MHz onboard clock to directly synthesize a 1MHz tone using the DDS core (v5). Pictures of fragments are below. 

 

fragments1.png
fragments2.png
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6,067 Views
Registered: ‎08-11-2016

Issue turned out not to be with the DDS core at all. I had a bug in the memory which caused only the first 1024 samples to be accessible, so those 1024 samples were just repeating in the plot. 

 

Thanks for the help everyone!

View solution in original post