I am using DDS Compiler to synthesize a variable frequency signal. Only Phase Generator is used, System Clock is 32.768 MHz, single channel and Phase Width is 12 bit. I am primarily targeting ISE 14.7 and DDS Compiler v4.0, but the problem also appears in Vivado 2018.2 and DDS Compiler v6.0. To demonstrate the problem I set Fixed Phase Increment mode and Fixed Phase Increment value = "100".
On the first page, the wizard shows Fs=32.768 000 000 000 001 (see the picture), but it should be exact (System Clock / Number of Channels) = 32.768.
Same numbers on the summary page.
I read the documents on this IP Core, including Known Issues, but didn't find anything about these small fraction parts. For me, it looks like there are rounding errors in the GUI, but I want to be extra sure that output files of this wizard will be correct.
So I am wondering, is this only a GUI issue? Will the generated core produce the correct output (0.032 MHz instead of 0.032+(something))?
Good question, I believe the GUI is correct, this is due to phase increment value and some other DDS configuration, the best way to get 32.768MHz is to enter 32.768 MHZ as the output frequence, then you can get the phase increment value with your current DDS paremeter configuration, you can send this phase increment value to DDS IP then you should be able to get the exact frequency you need.