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Participant rica.soles
Participant
534 Views
Registered: ‎06-01-2018

DDS Compiler

I need help with configurate the DDS compiler. I do my program in VHDL and i used de GUI for generate the core DDS. But i think it's wrong becouse when simulate not generate nothing. In sphase_td it must be see the value sin /cos in binary. Thanks you for your attention.VirtualBox_ISE_14.7_VIRTUAL_APPLIANCE_10_12_2018_23_05_36.png

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3 Replies
Moderator
Moderator
376 Views
Registered: ‎08-16-2018

Re: DDS Compiler

@rica.soles

You can run the attached "dds_tcl.tcl" (see tcl.jpg) to create the DDS project which is shown in "final_design_by_tcl.jpg" .

Next run the simulation to see the sine wave which is generated by DDS. 

 

Also, please see fig. 1.jpg to 3.jpg for settings and simulation results. 

 

tcl.jpg
final_design_by_tcl.jpg
1.jpg
2.jpg
3.jpg
Participant rica.soles
Participant
263 Views
Registered: ‎06-01-2018

Re: DDS Compiler

Thanks for you help but I´m working in ise desing, not in vivado.

Regards!!!

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254 Views
Registered: ‎06-21-2017

Re: DDS Compiler

Is sphase_tv an input to your DDS?  All inputs must be defined in your test bench for the output to be defined.

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