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ksram1988
Contributor
Contributor
468 Views
Registered: ‎07-16-2019

DDS IP Sinewave and Maximum Frequency

Hi

I am using ZCU111. The DAC sampling rate is set to is clocked at 500MSPS. I am using DDS IP to feed a sine wave to DAC and observe on CRO. I want to generate 

sine wave of frequency more than 100MHz. In order to check it, I wrote a verilog testbench for the DDS IP. I kept the system clock at 1GHz and output frequency of 200MHz. The following figures show the output waveform and settings of the design.

sinsim.PNGsinsim1.PNGsinsim2.PNGsinsim3.PNGsinsim4.PNGsinsim5.PNGsinsim6.PNG

My questions are -

1. Why am I not getting a Sine wave properly (smooth) in the simulation?

2. Is it possible to generate higher frequencies with DDS IP if sysclk is 1GHz? 

3. Is aclk and System clock of DDS IP one and the same? Can they be different? Which one needs to be higher if they are different?

4. From What I understand DDS can generate up to Fs/2 i.e upto 500MHz. If higher frequencies are supported and we feed it to DAC will we be able to see a smooth sine wave or something like a triangular wave (as frequencies increase)? 

5. If we want to see a higher frequency signal say at 200MHz, does the sampling rate of RFSoC DAC can stay at 500MSPS or does it need to be higher? 

 

Pease help.

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3 Replies
bruce_karaffa
Scholar
Scholar
442 Views
Registered: ‎06-21-2017

The waveform in the simulation is exactly what should be expected.  If you sample a 200MHz sine wave at 1 GHz, you will get 5 samples per cycle.  With only 5 samples, the waveform will not look smooth.  Think about what a sine wave with only two samples per cycle, it may be a triangular wave if sampled at the maxima and minima, or a straight line of sampled at the zero crossings.

ksram1988
Contributor
Contributor
249 Views
Registered: ‎07-16-2019

Hi @bruce_karaffa 

Does that mean I cannot produce a 200MHz Sinewave using DDS IP? Also please answer my further questions - 

 

2. Is it possible to generate higher frequencies with DDS IP if sysclk is 1GHz? 

3. Is aclk and System clock of DDS IP one and the same? Can they be different? Which one needs to be higher if they are different?

4. From What I understand DDS can generate up to Fs/2 i.e upto 500MHz. If higher frequencies are supported and we feed it to DAC will we be able to see a smooth sine wave or something like a triangular wave (as frequencies increase)? 

5. If we want to see a higher frequency signal say at 200MHz, does the sampling rate of RFSoC DAC can stay at 500MSPS or does it need to be higher? 

 

As I mentioned, I am working with ZCU111.

 

Please help.

 

Thank You

 

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drjohnsmith
Teacher
Teacher
241 Views
Registered: ‎07-09-2009

This might help

https://www.analog.com/en/analog-dialogue/articles/all-about-direct-digital-synthesis.html#

 

DDS is not magic, 

 

All its doing is producing amplitude samples of a sine wave cycle

    The more points you have in a single cycle, the more like a sine wave it will look in the time domain.

You need to be able to switch between the time and frequency domain when you think about digital sampling systems.

The link includes on the page a link to a dds design tool,

     where you can put in the sample frequency, and see the frequency response.

 

It shows the SIN(x)/(X) amplitude change, as well as the multiple harmonics that are generated and need to be filtered out of the output.

Also are links to other DDS  papers of interest,

 

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