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Observer rforsyth
Observer
4,697 Views
Registered: ‎03-25-2013

DDS Output rate too slow and staircased

Hello -

 

I have had this problem using both the FIR core gen and the DDS core gen where I am getting a staircased 6 microsecond output regardless of system clock frquency or output frequency settings.

 

The simpler case is the DDS, I have tested in a realtime system using a logic analyser and have tried system clock of both 20 Mhz and 120 Mhz, with output frequency setting of 1 Mhz , 20 Mhz and 60 Mhz with the output rate always fixed at approx 6 uSec per sample.

 

How can I get better resolution on the phase of the output? I see no reason that I shouldn't be able to get 16 nanosecond phase increments with a 120 MHz system clock.

DDSsteppy.png
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7 Replies
Observer rforsyth
Observer
4,695 Views
Registered: ‎03-25-2013

Re: DDS Output rate too slow and staircased

Here are the GUI inputs

DDS_GUI1.png
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Observer rforsyth
Observer
4,694 Views
Registered: ‎03-25-2013

Re: DDS Output rate too slow and staircased

 
DDS_GUI2.png
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Xilinx Employee
Xilinx Employee
4,693 Views
Registered: ‎08-02-2011

Re: DDS Output rate too slow and staircased

To be clear, you are changing both the core's system clock parameter AND the rate of the actual clock signal connected to the core?

Is this simulation? Can you post a pair of .xco files that you expect to be different and aren't?
www.xilinx.com
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Observer rforsyth
Observer
4,691 Views
Registered: ‎03-25-2013

Re: DDS Output rate too slow and staircased

Yes I am changing both the input clock (wired to input of core) and the parameter in the GUI

This is not a simulation - it is the actual logic analyser capture on an output test connector of the system under development, and yes the sampling rate is sufficient, I have sampled at 20 Mhz and at a finer resolution of 500Mhz.

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Observer rforsyth
Observer
4,689 Views
Registered: ‎03-25-2013

Re: DDS Output rate too slow and staircased

It isnt a matter of expecting the .xco's to be different, I just want one that works!

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Xilinx Employee
Xilinx Employee
4,656 Views
Registered: ‎11-28-2007

Re: DDS Output rate too slow and staircased

I would double check the input clock frequency to the DDS core running in HW. Bring it out to a pin and look at it on a scope.

 


@rforsyth wrote:

It isnt a matter of expecting the .xco's to be different, I just want one that works!




Cheers,
Jim
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Observer rforsyth
Observer
4,652 Views
Registered: ‎03-25-2013

Re: DDS Output rate too slow and staircased

 

Ok I tried a higher input clock as suggested - bumped it up to 180MHz and got a reasonable smooth output.

Then i gradually worked back down  - 160, 140 still looked good, then back to the original 120 and it looks good. So I really have no idea what fixed it or what was wrong.

 

 

Thanks for the input, resolved for now. If it reoccurs I will repost.

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