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Participant geschema1
Participant
1,559 Views
Registered: ‎12-28-2011

DDS Phase Dithering and Taylor Series Correction

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I have configured the DDS Compiler as follows:

 

  • System clock: 10 MHz
  • Phase width: 24 bits
  • Output width: 12 bits
  • Phase angle width (computed by DDS compiler): 12 bits

Without any noise shaping, DDS Compiler reports an SFDR of 72 dB

 

Using the same DDS configuration, I noticed that enabling the noise shaping features either have no effect (with phase dithering enabled, I still get a SFDR of 72 dB) or give worse SFDRs (66 dB for Taylor series correction). In my understanding, noise shaping is supposed to increase SFDR. Am I missing something?

 

 

 

 

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Xilinx Employee
Xilinx Employee
2,146 Views
Registered: ‎08-01-2008

Re: DDS Phase Dithering and Taylor Series Correction

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check page 41 figure 4-1 to understand relationship
https://www.xilinx.com/support/documentation/ip_documentation/dds_compiler/v6_0/pg141-dds-compiler.pdf
Thanks and Regards
Balkrishan
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2 Replies
Xilinx Employee
Xilinx Employee
2,147 Views
Registered: ‎08-01-2008

Re: DDS Phase Dithering and Taylor Series Correction

Jump to solution
check page 41 figure 4-1 to understand relationship
https://www.xilinx.com/support/documentation/ip_documentation/dds_compiler/v6_0/pg141-dds-compiler.pdf
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Participant geschema1
Participant
1,534 Views
Registered: ‎12-28-2011

Re: DDS Phase Dithering and Taylor Series Correction

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Thanks @balkris. That's useful information.

 

The thing that confused me was that turning phase dithering on did not increase SFDR. That's because when enablling dithering, DDS compiler automatically reduces the truncated phase word length by two bits, which yields the same SFDR as the original truncated phase word length with dithering off.

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