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Registered: ‎02-24-2010

DDS compiler 2.1 problem in System generator


I had initially a design in System Generator that compiled suceesfully. When I changed the output frequency
in a DDS compiler 2.1 block from 37.28 to 10 MHz the compilation failed even though the system could still
be simulated in Simulink. The reason given by System Generator is "standard exception" as below  

standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: couldn't run
c:/xilinx/10.1/ise/bin/nt/coregen.exe: 1 at C:\Xilinx system
generator 10.1
line 715

I looked at coregen log file and the following error was at the end:

ERROR:coreutil - Exception caught when running XST synthesis!
ERROR:coreutil - Failure to generate output products
ERROR:coreutil:424 - An error occurred while running Java. Please examine the
   console or coregen log file for a specific IP related error.
    For more information please search the Xilinx Answers Database for this
   error: Regenerating.
ERROR:sim:57 - Error found during generation

I am using ISE foundation and System Generator 10.1, update 3. The settings in DDS compiler 2.1 are:
clock frequency 100 MHz, sample period 1e-8 (same as Simulink system period), spurious free dynamic range 36,
frequency resolution 0.4.

I also tried using diffrenet output frequencies like 37.18 MHz but that also doesn't work! It's simply stuck a 37.28 MHz
If I go back to 37.28 it works ! Seems quite bizzare, I tried reseting my computer, Matlab, changing file names etc
but it didn't work. What could be wrong here?

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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2007

Re: DDS compiler 2.1 problem in System generator

I recommend opening a case with the Xilinx Technical Support for this issue.

Versal ACAP: AI Engines | Embedded SW Support

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