09-15-2020 05:43 AM
Hi , I am using DDS compiler to generate IQ data. I am observing that this IP cannot generate an output frequency higher than the input frequency(clock system). I am very grateful if any person can give any idea to generate a higher frequency than the input. I need to have an output more than 2.6 GHz. Thanks a lot for any idea. I am grateful a lot.
09-16-2020 12:02 PM
We can not generate the output frequency greater than system frequency.
Below is equation for output frequency which can be generated by DDS IP. More details are provided in pg141,
output frequency = system frequency * N/M, where 0 < N < M
09-18-2020 12:20 AM
Hi @JKdevelloper1 ,
If you are using System Generator for DSP tool, it has a block called Vector DDFS block which allows generation of high frequencies which are beyond clock frequency using Super sample rate technique.
Like Meher commented, with DDS compiler it is not possible for frequency greater than clock frequency which is the Fs for block (Nyquist rule !!!).
09-18-2020 04:49 AM
Consider what @vkanchan said about the Vector DDFS block in System Generator. Look into it and decide if that would work for you.
"please can you tell me if this block allows you me to generate IQ data running at GHZ or not."
Given that it generates multiple samples per clock, the answer is probably. However you have to put forth the effort to determine this.
One hint: the RFDC axis interface uses a FPGA fabric interface that includes multiple samples per clock, so the DAC side can receive higher rate data suitable for transmission in Nyquist bands 1 or 2. Therefore if you use System Generator or roll your own DDS that produces multiple samples per clock you can generate higher frequency data, at a GHz rate. Think about it.