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vizziee
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Registered: ‎10-21-2009

DDS core output is different when observed on Chipscope Pro

Hello,

 

I am using three single-channel DDS cores in my design and all of them are clocked at 200 MHz. The other parameters are as follows: SFDR = 90 dB, Phase dithering = enabled. The 16-bit outputs are both SIN and COS.

 

During functional simulation in ModelSim, the output waveforms are just as expected and very consistent. However when I observe them on Chipscope Pro, I see that while the output values of DDS largely match bit-by-bit with the ones shown in the simulation, it does differ at a few points. The exact samples when this mismatch occurs differs with each different compilation of the entire design.

 

Initially I thought this could be related to the larger depth of the ChipscopePro. However, when I collected the data over a bus on my computer (the ChipscopePro was still connected to the core), even that data showed such glitches in the DDS output. I don't think this is an expected behavior as the data that I am observing is straight from the DDS core and doesn't go through any additional user-logic.

 

I doubt if this is related with 200MHz clock - it is fairly well-within the high0frequency limits. Also, usually the timing score of my compiled design is zero or very low (<20).

 

Any help regarding this issue would be greatly appreciated.

 

Regards,

 

Kumar Vijay Mishra.

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vizziee
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Registered: ‎10-21-2009

Hello,

 

Here are a few images related to my problem. In the first image (dds_modelsim), the outputs of the three DDS modules (at frequencies f1, f2 and f3) are shown as simulated in ModelSim. For simplicity I have not included the cosine waveforms of the other two DDS modules.

 

In the second image (dds_chipscopepro_8192), outputs as observed on ChipscopePro (when ILA is set to capture 8192 samples) is shown. The compiled design had a timing score of zero.

 

In the third image (dds_chipscopepro_2048), outputs as observed on ChipscopePro (when ILA is set to capture 2048 samples) is shown. The compiled design has a low timing score of zero.

 

As can be seen from these images the output samples observed on Chiscope Pro are either shifted in time (with respect to each other eg. sine_f3 in dds_chipscopepro_9192 is shifted by 1 sample with respect to the other signals) or are different than their expected values (eg. third sample of cosine_f1 has a value of 986D instead of the expected 9874 in ModelSim). All three DDS are completely identical and differ only in their output frequency (which are 60 MHz, 70 MHz and 50MHz respectively). The .vhd file of the dds module is also attached here. There is no additional logic in output of the core before I capture them on ChipscopePro.

 

Regards, 

 

Kumar Vijay Mishra.

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ywu
Xilinx Employee
Xilinx Employee
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Registered: ‎11-28-2007

At the risk of stating the obvious, the way that the phase dithering works is to add a RANDOM noise to the phase value. You wouldn't see the exact match at DDS output if you capture the data at different time.
Cheers,
Jim
vizziee
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Registered: ‎10-21-2009

Hi jimwu,

 

Thanks for your reply.

 

Its true that the phase dithering should add the random noise to the phase value. But then this leads me to a few simple questions:

 

a. Random noise should only change the value of the output not the relative time at which these outputs appear. If you see the image files that I have attached, the relative time of the signals is different than that in simulation (e.g. sine_f3 in dds_chipscopepro_8192.png is shifted by 1 sample with respect to the other signals).

b. I would assume that random noise is not hard-coded in the design and hence, outputs should be different if I clear the dds core and re-capture the data. However, this doesn't happen. I am capturing the data in the ChipscopePro by triggering it with a periodic pulse signal. This pulse also clears the dds each time it appears. The data so captured after this trigger is always the SAME (though different than the data observed in ModelSim) for a given compilation. Does that mean that the random noise gets hard-coded for a given compilation?

 

Regards,

 

Kumar Vijay Mishra.

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vizziee
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Registered: ‎10-21-2009

Hello All,

 

An update from my side on this issue:

 

Here is a quick Screenshot of dds outputs as observed on ChipscopePro when I removed all other submodules and kept only dds in the design. The timing score for the compilation was zero. As you can see, the output of the dds is perfectly similar to the functional simulation.

If the timing score remains zero in the dds-only design as well as the complete design, why should the behavior of the dds change in the latter case?

 

Thanks and regards,

 

Kumar Vijay Mishra.

dds_only_ChipscopePro.png
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