UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer kbkien
Observer
2,851 Views
Registered: ‎12-07-2012

DDS generates quarter/half wave?

Jump to solution

Hi all,

 

I used coregen to generate a dds as below parameters:

f_clk = 150 MHz

f_output = 150 MHz

B_n = 16 bits

 

I am interested on the sine/consine waveform and I have performed a simulation on modelsim. What I noticed was the sine wave generated by dds is always positive values which isn't a a full sine wave.

 

Is the dds only generated half/quarter of the sine wave? If so, I guess I need extra logics to get it work in a full cycle.

 

Thanks.

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
3,096 Views
Registered: ‎08-02-2011

Re: DDS generates quarter/half wave?

Jump to solution

Are you interpreting the output data as 2's complement?

www.xilinx.com

View solution in original post

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
3,097 Views
Registered: ‎08-02-2011

Re: DDS generates quarter/half wave?

Jump to solution

Are you interpreting the output data as 2's complement?

www.xilinx.com

View solution in original post

0 Kudos
Observer kbkien
Observer
2,839 Views
Registered: ‎12-07-2012

Re: DDS generates quarter/half wave?

Jump to solution

Yes. I've solved it by reducing the number of bits (phase) from 16 to 10. And it works. Don't exactly understand what happened.

 

 

0 Kudos