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Observer kbkien
Observer
9,073 Views
Registered: ‎12-07-2012

DDS questions.

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I used coregen to generate a DDS as below parameters:

f_clk = 250 MHz

f_output = 62.5 MHz (= 250/4)

B_n = 18 bits

phase_increment = 65536

 

To ensure I have a correct sine wave frequency, I have performed a simulation using Modelsim. My understanding is, a full cycle sine wave (output) should be completed within 4 clock cycles for such system. However, the output of the sine wave from my simulation used 408 clock cycles for a complete sine wave. I have read the data sheet twice and can't really understanfd why. I would be greatly appreciate if someone can help me. Thank you very much.

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1 Solution

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Xilinx Employee
Xilinx Employee
10,735 Views
Registered: ‎11-28-2007

Re: DDS questions.

Jump to solution

The clock is too fast. Change the period to something like 10ns and run it again. It would help if you can attach your complete project with the dds core in it. Also change the radix of dds output to signed number.


@kbkien wrote:

This is my testbench. The funny part is the phase_tdata is 0.

 

 

module dds_tb;

reg                 clk          = 0;
reg                 conf_in_tvld = 1;
wire                data_out_tvld;
wire                phase_out_tvld;
reg         [23:0]  conf_in_tdata = {6'd0,18'd65536};
wire        [15:0]  data_out_tdata;
wire        [23:0]  phase_out_tdata;
wire signed [15:0]  sine;


// Generate clock
always #1 clk = !clk;

// DUT
dds DUT(
  .aclk                 (clk),
  .s_axis_config_tvalid (conf_in_tvld),
  .m_axis_data_tvalid   (data_out_tvld),
  .m_axis_phase_tvalid  (phase_out_tvld),
  .s_axis_config_tdata  (conf_in_tdata),
  .m_axis_data_tdata    (data_out_tdata),
  .m_axis_phase_tdata   (phase_out_tdata)
);

assign sine = $signed(data_out_tdata);

endmodule




Cheers,
Jim
10 Replies
Scholar austin
Scholar
9,068 Views
Registered: ‎02-27-2008

Re: DDS questions.

Jump to solution

k,

 

So, you have exactly 4 samples in this:  since on each clock you add 1/4 cycle (to get a divide by 4 of 250 MHz).  This is not a good sign wave (0, +1, 0, -1, ....).  If this is all you want, you could do it with a counter.

 

Given those numbers, I see no way that you have 408 clock cycles for anything at all:  in four clocks you are back to 0.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer kbkien
Observer
9,061 Views
Registered: ‎12-07-2012

Re: DDS questions.

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Thanks for your reply.I thought f_clk > 2*f_output to follow the nyquist sampling theorem?

 

I intend to have a dds which can generate sine wave with different frequencies and 250/4 MHz is one of them.

 

 

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Scholar austin
Scholar
9,052 Views
Registered: ‎02-27-2008

Re: DDS questions.

Jump to solution

k,

 

Well, it is true that four sample satisfies the Nyquist Sampling Rate requirement, but it is not nearly fast enough for any fidelity requirements (harmonic distortion, etc.).

 

If you require a sine wave, then you need perhaps 1024 points, minimum for a ful cycle, or 256 points for the quarter  cycle (is sufficient storage).  That means the highesdt frequency sine wave you may generate is ~Fclk/1000.

 

An alternative is to use the MSB of the phase accumulator as the output directly to a PLL.  The PLL is then set to oscillate in a narrow range about the Fout of the phase accumulator.  When locked, the VCO is then used directly (assuming a sine wave voltage controlled oscillator).  I doubt seriously you get a sine wave from 0 to 63 MHz by any means that doesn't involve switching sources, filters, methods, etc.

 

There is a reason why good bench test equipment oscillators cost so much money....

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Instructor
Instructor
9,050 Views
Registered: ‎08-14-2007

Re: DDS questions.

Jump to solution

Did you use a fixed phase increment when you generated the core?  Or did you

generate the core with a phase increment input port and supply the phase increment

in your test bench?  If you really have an 18-bit accumulator, then you'd need a phase

increment of about 643 instead of 65536 to generate a sine wave in 408 clocks.

If you used a fixed phase increment, I'd go back through the core setup again

and make sure it has the correct values for input and output frequency and accumulator

bits.

 

-- Gabor

-- Gabor
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Observer kbkien
Observer
9,035 Views
Registered: ‎12-07-2012

Re: DDS questions.

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Thanks for the replies. It is a programmable phase increment. I regenerated the core again and it showed the same results.

 

Any suggestions?

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Xilinx Employee
Xilinx Employee
9,031 Views
Registered: ‎11-28-2007

Re: DDS questions.

Jump to solution

Please post the waveform with all signals to/from the DDS core. Sometimes the waveform can be deceiving when it comes to the frequency components in the signal.

 


@kbkien wrote:

Thanks for the replies. It is a programmable phase increment. I regenerated the core again and it showed the same results.

 

Any suggestions?




Cheers,
Jim
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Observer kbkien
Observer
9,020 Views
Registered: ‎12-07-2012

Re: DDS questions.

Jump to solution

This is my testbench. The funny part is the phase_tdata is 0.

 

 

module dds_tb;

reg                 clk          = 0;
reg                 conf_in_tvld = 1;
wire                data_out_tvld;
wire                phase_out_tvld;
reg         [23:0]  conf_in_tdata = {6'd0,18'd65536};
wire        [15:0]  data_out_tdata;
wire        [23:0]  phase_out_tdata;
wire signed [15:0]  sine;


// Generate clock
always #1 clk = !clk;

// DUT
dds DUT(
  .aclk                 (clk),
  .s_axis_config_tvalid (conf_in_tvld),
  .m_axis_data_tvalid   (data_out_tvld),
  .m_axis_phase_tvalid  (phase_out_tvld),
  .s_axis_config_tdata  (conf_in_tdata),
  .m_axis_data_tdata    (data_out_tdata),
  .m_axis_phase_tdata   (phase_out_tdata)
);

assign sine = $signed(data_out_tdata);

endmodule

dds_comp_v4.jpg
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Observer kbkien
Observer
9,018 Views
Registered: ‎12-07-2012

Re: DDS questions.

Jump to solution
In addition, there isn't negative part of the wave. I guess coregen only creates half sine wave.
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Xilinx Employee
Xilinx Employee
10,736 Views
Registered: ‎11-28-2007

Re: DDS questions.

Jump to solution

The clock is too fast. Change the period to something like 10ns and run it again. It would help if you can attach your complete project with the dds core in it. Also change the radix of dds output to signed number.


@kbkien wrote:

This is my testbench. The funny part is the phase_tdata is 0.

 

 

module dds_tb;

reg                 clk          = 0;
reg                 conf_in_tvld = 1;
wire                data_out_tvld;
wire                phase_out_tvld;
reg         [23:0]  conf_in_tdata = {6'd0,18'd65536};
wire        [15:0]  data_out_tdata;
wire        [23:0]  phase_out_tdata;
wire signed [15:0]  sine;


// Generate clock
always #1 clk = !clk;

// DUT
dds DUT(
  .aclk                 (clk),
  .s_axis_config_tvalid (conf_in_tvld),
  .m_axis_data_tvalid   (data_out_tvld),
  .m_axis_phase_tvalid  (phase_out_tvld),
  .s_axis_config_tdata  (conf_in_tdata),
  .m_axis_data_tdata    (data_out_tdata),
  .m_axis_phase_tdata   (phase_out_tdata)
);

assign sine = $signed(data_out_tdata);

endmodule




Cheers,
Jim
Observer kbkien
Observer
3,319 Views
Registered: ‎12-07-2012

Re: DDS questions.

Jump to solution

You are absolutely right! The clock is too fast. Thank you so much for your help.

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