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Visitor nikbartrz
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2,370 Views
Registered: ‎11-23-2017

DPD maximum instantaneous bandwidth

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Hi, given the fact that I was denied the access to the evaluation lounge of the DPD IP core (I can't access the core's documentation), I would like to make the following questions based on the short description of the DPD IP core given here https://www.xilinx.com/products/intellectual-property/ef-di-dpd.html.

In that page it is claimed that the "Maximum instantaneous bandwidth" of the core is "400MHz".

 

Hence, if I have a custom multicarrier signal with 400 MHz BW can I use the DPD IP core to pre-distort it up to he third intermodulation (IM3) product?

If then I want to use more than one antenna paths (e.g., 8 channels), does this affect the "maximum instantaneous bandwidth of 400MHz"?

In other words, can I pre-distort  8 signals of 400 MHz (in a 8 transmit antennas scheme) up to the IM3 using the DPD IP core?

 

Thanks in advance for your time.

Nikos

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Visitor nikbartrz
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3,083 Views
Registered: ‎11-23-2017

Re: DPD maximum instantaneous bandwidth

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For the people interested to know the answer to my question: I got an answer by email specifying that for the V8.0 of the DPD core (Zynq Ultrascale+):

Maximum iBW = 200 MHz

{Clocks Per Sample}[Phase] = 1 [1], 1 [1, 2]

Max Clock Support = 614.4MHz

Max Sampling Rate = 983.04MSps

Datapath Interface = Waveform Agnostics (No framing information needed)

 

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Mentor jmcclusk
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Registered: ‎02-24-2014

Re: DPD maximum instantaneous bandwidth

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400 MHz maximum bandwidth is probably based on a 400 MHz sample rate on a complex path (I & Q) with no oversampling.   That's a fairly ambitious clock rate, and assumes that the FPGA is not overly packed, and that you aren't using the slowest speed grade of Virtex or Kintex.   It would apply to each channel that you are processing, so yes,  you could handle 8 channels that way for a MIMO application.  I would probably derate things a bit, and allow for some oversampling margin, like 2:1, so that would reduce the effective bandwidth by 2.    There's nothing preventing a parallel implementation of the Volterra kernel, so an alternate design could exceed these bandwidth limits with parallel data paths.

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Visitor nikbartrz
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Registered: ‎11-23-2017

Re: DPD maximum instantaneous bandwidth

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Thank's a lot for the answer. I forgot to mention that the target device I am considering is the one fitted in the ZCU102 Evaluation Kit (speed grade -2) which apart from the DPD will also host a custom CFR block and also a CPRI interface. So yes, I would assume that there would be sufficient space there (hopefully the logic would not be congested) considering that for an 8 antenna system we would need to partition the overall implementation in 4 ZCU102 boards (1 DPD core serving 2 antennas per board).

Having said that, if I take for granted the specs of the DPD IP core (mentioned in the webpage), I suppose that there are some practical limits in the clock that can feed the parallelized implementation of the Xilinx DPD core. Hence the question still applies:

Up to which intermodulation product can I predistort a 400 MHz complex signal considering as well that I need to have 2 of them in parallel (when applying the MIMO setup mentioned before)?

In a practical DPD system (without any polyphase parallelization and DDR technique applied) linearizing a 400 MHz signal up to IM5 would imply 2000 MSPS sampling rate (hence a 2 GHz internal DPD clock), which would need to be processed instantaneously by the DPD core (out of question with today's technology). Unfortunately, without the product guide it's difficult to avoid questions like the ones I am posting here.

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Mentor jmcclusk
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Registered: ‎02-24-2014

Re: DPD maximum instantaneous bandwidth

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Talk to your local Xilinx distributor FAE, and ask him to get you access to the documentation. Unless you are in a country on the State Department "naughty" list, there's shouldn't be a problem getting access.

Don't forget to close a thread when possible by accepting a post as a solution.
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Visitor nikbartrz
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Registered: ‎11-23-2017

Re: DPD maximum instantaneous bandwidth

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I did contact Xilinx and waiting for an answer. I have been using the Xilinx toolchain and buying Xilinx boards for more than 14 years (while living in the UK and now in Spain). As far as I know, in neither of the two countries apply any restrictions (I did evaluate other IP cores in the past). Thanks for your advice :-)

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: DPD maximum instantaneous bandwidth

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Refer to DPD data sheet, A general guideline is that the pre-distortion bandwidth fs should be at least five times the signal bandwidth. However factors such as the PA design, the degree of correction required and the signal type come into play.
so 122.88Mbps is no problem for LTE 20MHz. 
 
Max Sampling Rate 983.04MSps supported by DPD v8.1
 
Here is the recommend clock frequency based on 122.88Mbps sample rate.
 
Maximum iBW 200 MHz
 
Thanks and Regards
Balkrishan
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Visitor nikbartrz
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Registered: ‎11-23-2017

Re: DPD maximum instantaneous bandwidth

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Thanks for replying. I am afraid though that my question remains unanswered.

I was not enquiring about a 20 MHz (30.72 MSPS) LTE signal (btw, I went through the AR before posting my question).

Can the DPD core of Xilinx linearize a signal featuring up to 400 MHz instantaneous bandwidth as it is indicated in the webpage of the IP core?

If yes, up to which intermodulation product can the DPD predistort a 400 MHZ (I guess the correct notion here MSPS) signal?

Best regards,

Nikos

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Visitor nikbartrz
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3,084 Views
Registered: ‎11-23-2017

Re: DPD maximum instantaneous bandwidth

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For the people interested to know the answer to my question: I got an answer by email specifying that for the V8.0 of the DPD core (Zynq Ultrascale+):

Maximum iBW = 200 MHz

{Clocks Per Sample}[Phase] = 1 [1], 1 [1, 2]

Max Clock Support = 614.4MHz

Max Sampling Rate = 983.04MSps

Datapath Interface = Waveform Agnostics (No framing information needed)

 

View solution in original post

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